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p89c660/p89c662/p89c664/p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram product data replaces p89c660/p89c662/p89c664 of 2001 jul 19 and p89c668 of 2001 jul 27 2002 oct 28 integrated circuits
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2 2002 oct 28 853-2392 29118 description the p89c660/662/664/668 device contains a non-volatile 16kb/32kb/64kb flash program memory that is both parallel programmable and serial in-system and in-application programmable. in-system programming (isp) allows the user to download new code while the microcontroller sits in the application. in-application programming (iap) means that the microcontroller fetches new program code and reprograms itself while in the system. this allows for remote programming over a modem link. a default serial loader (boot loader) program in rom allows serial in-system programming of the flash memory via the uart without the need for a loader in the flash code. for in-application programming, the user program erases and reprograms the flash memory by use of standard routines contained in rom. this device executes one instruction in 6 clock cycles, hence providing twice the speed of a conventional 80c51. an otp configuration bit gives the user the option to select conventional 12-clock timing. this device is a single-chip 8-bit microcontroller manufactured in advanced cmos process and is a derivative of the 80c51 microcontroller family. the instruction set is 100% executing and timing compatible with the 80c51 instruction set. the device also has four 8-bit i/o ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced uart and on-chip oscillator and timing circuits. the added features of the p89c660/662/664/668 makes it a powerful microcontroller for applications that require pulse width modulation, high-speed i/o and up/down counting capabilities such as motor control. features ? 80c51 central processing unit ? on-chip flash program memory with in-system programming (isp) and in-application programming (iap) capability ? boot rom contains low level flash programming routines for downloading via the uart ? can be programmed by the end-user application (iap) ? parallel programming with 87c51 compatible hardware interface to programmer ? six clocks per machine cycle operation (standard) ? 12 clocks per machine cycle operation (optional) ? speed up to 20 mhz with 6 clock cycles per machine cycle (40 mhz equivalent performance); up to 33 mhz with 12 clocks per machine cycle ? fully static operation ? ram externally expandable to 64 kbytes ? four interrupt priority levels ? eight interrupt sources ? four 8-bit i/o ports ? full-duplex enhanced uart framing error detection automatic address recognition ? power control modes clock can be stopped and resumed idle mode power-down mode ? programmable clock out ? second dptr register ? asynchronous port reset ? low emi (inhibit ale) ? i 2 c serial interface ? programmable counter array (pca) pwm capture/compare ? well-suited for ipmi applications
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 3 selection table type memory timers serial inter- faces ram rom otp flash # of timers pwm pca wd uart i 2 c can spi adc bits/ch. i/o pins interrupts (external) program security default clock rate optional clock rate reset active low/high? max. freq. at 6-clk / 12-clk (mhz) freq. range at 3v (mhz) freq. range at 5v (mhz) p89c668 8k 64k 4 32 8(2)/4 6-clk 12-clk h 20/33 0-20/33 p89c664 2k 64k 4 32 8(2)/4 6-clk 12-clk h 20/33 0-20/33 p89c662 1k 32k 4 32 8(2)/4 6-clk 12-clk h 20/33 0-20/33 p89c660 512b 16k 4 32 8(2)/4 6-clk 12-clk h 20/33 0-20/33 ordering information memory temperature range ( c) voltage frequency (mhz) device flash ram temperature range ( c) and package voltage range 6 clock mode 12 clock mode dwg # p89c660hba 16 kb 512 b 0 to +70, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 p89c660hfa 16 kb 512 b 40 to +85, plcc 4.755.25 v 0 to 20 mhz 0 to 33 mhz sot187-2 p89c660hbbd 16 kb 512 b 0 to +70, lqfp 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot389-1 p89c662hba 32 kb 1 kb 0 to +70, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 p89c662hfa 32 kb 1 kb 40 to +85, plcc 4.755.25 v 0 to 20 mhz 0 to 33 mhz sot187-2 p89c662hbbd 32 kb 1 kb 0 to +70, lqfp 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot389-1 p89c662hfbd 32 kb 1 kb 40 to +85, lqfp 4.755.25 v 0 to 20 mhz 0 to 33 mhz sot389-1 p89c664hba 64 kb 2 kb 0 to +70, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 p89c664hfa 64 kb 2 kb 40 to +85, plcc 4.755.25 v 0 to 20 mhz 0 to 33 mhz sot187-2 p89c664hbbd 64 kb 2 kb 0 to +70, lqfp 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot389-1 p89c664hfbd 64 kb 2 kb 40 to +85, lqfp 4.755.25 v 0 to 20 mhz 0 to 33 mhz sot389-1 p89c668hba 64 kb 8 kb 0 to +70, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 p89c668hfa 64 kb 8 kb 40 to +85, plcc 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot187-2 p89c668hbbd 64 kb 8 kb 0 to +70, lqfp 4.55.5 v 0 to 20 mhz 0 to 33 mhz sot389-1
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 4 block diagram 1 su01713 accelerated 80c51 cpu 6-clk mode (default) 12-clk mode (optional) 16k / 32k / 64 kbyte code flash 0.5k / 1k / 2k / 8 kbyte data ram port 3 configurable i/os port 2 configurable i/os port 1 configurable i/os port 0 configurable i/os oscillator crystal or resonator full-duplex enhanced uart timer 0 timer 1 timer 2 programmable counter array (pca) watchdog timer i 2 c interface
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 5 block diagram (cpu-oriented) su01089 psen ea /v pp ale rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register ram port 0 latch port 2 latch flash register b acc stack pointer tmp2 tmp1 alu timing and control instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr's multiple p1.0p1.7 p3.0p3.7 p0.0p0.7 p2.0p2.7 sfrs timers p.c.a. 8 8 16 i 2 c scl sda
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 6 logic symbol port 0 port 1 port 2 port 3 address and data bus address bus t2 t2ex rxd txd int0 int1 t0 t1 wr rd secondary functions rst ea /v pp psen ale/prog v ss v cc xtal1 xtal2 su01090 scl sda pinning plastic leaded chip carrier su01091 plcc 6140 7 17 39 29 18 28 pin function 1 nic* 2 p1.0/t2 3 p1.1/t2ex 4 p1.2/eci 5 p1.3/cex0 6 p1.4/cex1 7 p1.5/cex2 8 p1.6/scl 9 p1.7/sda 10 rst 11 p3.0/rxd 12 nic* 13 p3.1/txd 14 p3.2/int0 15 p3.3/int1 pin function 16 p3.4/t0/cex3 17 p3.5/t1/cex4 18 p3.6/wr 19 p3.7/rd 20 xtal2 21 xtal1 22 v ss 23 nic* 24 p2.0/a8 25 p2.1/a9 26 p2.2/a10 27 p2.3/a11 28 p2.4/a12 29 p2.5/a13 30 p2.6/a14 pin function 31 p2.7/a15 32 psen 33 ale 34 nic* 35 ea /v pp 36 p0.7/ad7 37 p0.6/ad6 38 p0.5/ad5 39 p0.4/ad4 40 p0.3/ad3 41 p0.2/ad2 42 p0.1/ad1 43 p0.0/ad0 44 v cc * no internal connection low quad flat pack su01401 lqfp 44 34 1 11 33 23 12 22 pin function 1 p1.5/cex2 2 p1.6/scl 3 p1.7/sda 4 rst 5 p3.0/rxd 6 nic* 7 p3.1/txd 8 p3.2/int0 9 p3.3/int1 10 p3.4/t0/cex3 11 p3.5/t1/cex4 12 p3.6/wr 13 p3.7/rd 14 xtal2 15 xtal1 pin function 16 v ss 17 nic* 18 p2.0/a8 19 p2.1/a9 20 p2.2/a10 21 p2.3/a11 22 p2.4/a12 23 p2.5/a13 24 p2.6/a14 25 p2.7/a15 26 psen 27 ale 28 nic* 29 ea /v pp 30 p0.7/ad7 pin function 31 p0.6/ad6 32 p0.5/ad5 33 p0.4/ad4 34 p0.3/ad3 35 p0.2/ad2 36 p0.1/ad1 37 p0.0/ad0 38 v cc 39 nic* 40 p1.0/t2 41 p1.1/t2ex 42 p1.2/eci 43 p1.3/cex0 44 p1.4/cex1 * no internal connection
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 7 pin descriptions mnemonic pin number type name and function mnemonic plcc lqfp type name and function v ss 22 16 i ground: 0 v reference. v cc 44 38 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.00.7 4336 3730 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. p1.0p1.7 29 4044, 13 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups on all pins except p1.6 and p1.7 which are open drain. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). alternate functions for p89c660/662/664/668 port 1 include: 2 40 i/o t2 (p1.0): timer/counter 2 external count input/clockout (see programmable clock-out) 3 41 i t2ex (p1.1): timer/counter 2 reload/capture/direction control 4 42 i eci (p1.2): external clock input to the pca 5 43 i/o cex0 (p1.3): capture/compare external i/o for pca module 0 6 44 i/o cex1 (p1.4): capture/compare external i/o for pca module 1 7 1 i/o cex2 (p1.5): capture/compare external i/o for pca module 2 8 2 i/o scl (p1.6): i 2 c bus clock line (open drain) 9 3 i/o sda (p1.7): i 2 c bus data line (open drain) p2.0p2.7 2431 1825 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (mov @ri), port 2 emits the contents of the p2 special function register. p3.0p3.7 11, 1319 5, 713 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also serves the special features of the p89c660/662/664/668, as listed below: 11 5 i rxd (p3.0): serial input port 13 7 o txd (p3.1): serial output port 14 8 i int0 (p3.2): external interrupt 15 9 i int1 (p3.3): external interrupt 16 10 i cex3/t0 (p3.4): timer 0 external input; capture/compare external i/o for pca module 3 17 11 i cex4/t1 (p3.5): timer 1 external input; capture/compare external i/o for pca module 4 18 12 o wr (p3.6): external data memory write strobe 19 13 o rd (p3.7): external data memory read strobe rst 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal resistor to v ss permits a power-on reset using only an external capacitor to v cc . ale 33 27 o address latch enable: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted twice every machine cycle, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ale can be disabled by setting sfr auxiliary.0. with this bit set, ale will be active only during a movx instruction. psen 32 26 o program store enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 8 mnemonic name and function type pin number mnemonic name and function type lqfp plcc ea /v pp 35 29 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations. if ea is held high, the device executes from internal program memory. the value on the ea pin is latched when rst is released and any subsequent changes have no effect. this pin also receives the programming supply voltage (v pp ) during flash programming. xtal1 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 20 14 o crystal 2: output from the inverting oscillator amplifier. note: to avoid alatch-upo effect at power-on, the voltage on any pin (other than v pp ) must not be higher than v cc + 0.5 v or less than v ss 0.5 v.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 9 table 1. special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h auxr# auxiliary 8eh extram ao xxxxxx10b auxr1# auxiliary 1 a2h enboot gf2 0 dps xxxxx0x0b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ccap0h# module 0 capture high fah xxxxxxxxb ccap1h# module 1 capture high fbh xxxxxxxxb ccap2h# module 2 capture high fch xxxxxxxxb ccap3h# module 3 capture high fdh xxxxxxxxb ccap4h# module 4 capture high feh xxxxxxxxb ccap0l# module 0 capture low eah xxxxxxxxb ccap1l# module 1 capture low ebh xxxxxxxxb ccap2l# module 2 capture low ech xxxxxxxxb ccap3l# module 3 capture low edh xxxxxxxxb ccap4l# module 4 capture low eeh xxxxxxxxb ccapm0# module 0 mode c2h ecom capp capn mat tog pwm eccf x0000000b ccapm1# module 1 mode c3h ecom capp capn mat tog pwm eccf x0000000b ccapm2# module 2 mode c4h ecom capp capn mat tog pwm eccf x0000000b ccapm3# module 3 mode c5h ecom capp capn mat tog pwm eccf x0000000b ccapm4# module 4 mode c6h ecom capp capn mat tog pwm eccf x0000000b c7 c6 c5 c4 c3 c2 c1 c0 ccon*# pca counter control c0h cf cr ccf4 ccf3 ccf2 ccf1 ccf0 00x00000b ch# pca counter high f9h 00h cl# pca counter low e9h 00h cmod# pca counter mode c1h cidl wdte cps1 cps0 ecf 00xxx000b dptr: data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ec es1 es0 et1 ex1 et0 ex0 00h ien1* interrupt enable 1 e8 et2 xxxxxxx0b bf be bd bc bb ba b9 b8 ip* interrupt priority b8h pt2 ppc ps1 ps0 pt1 px1 pt0 px0 x0000000b iph# interrupt priority high b7h pt2h ppch ps1h ps0h pt1h px1h pt0h px0h x0000000b 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1* port 1 90h sda scl cex2 cex1 cex0 eci t2ex t2 ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ffh b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1/ cex4 t0/ cex3 int1 int0 txd rxd ffh pcon# 1 power control 87h smod1 smod0 pof gf1 gf0 pd idl 00xxx000b * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. reserved bits. 1. reset value depends on reset source.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 10 table 1 special function registers (continued) symbol description direct address bit address, symbol, or alternative port function msb lsb reset value d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00000000b rcap2h # timer 2 capture high cbh 00h rcap2l # timer 2 capture low cah 00h saddr# slave address a9h 00h saden# slave address mask b9h 00h s0buf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 s0con* serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h s1dat# serial 1 data dah 00h s1adr# serial 1 address dbh slave address gc 00h s1sta# serial 1 status d9h sc4 sc3 sc2 sc1 sc0 0 0 0 f8h df de dd dc db da d9 d8 s1con*# serial 1 control d8h cr2 ens1 sta sto si aa cr1 cr0 00000000b 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2con* timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 00h t2mod# timer 2 mode control c9h t2oe dcen xxxxxx00b th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h th2# timer high 2 cdh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tl2# timer low 2 cch 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h wdtrst watchdog timer reset a6h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. reserved bits. oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. minimum and maximum high and low times specified in the data sheet must be observed. this device is configured at the factory to operate using 6 clock periods per machine cycle, referred to in this datasheet as a6 clock modeo. (this yields performance equivalent to twice that of standard 80c51 family devices). it may be optionally configured on commercially-available eprom programming equipment to operate at 12 clock periods per machine cycle, referred to in this datasheet as a12 clock modeo. once 12 clock mode has been configured, it cannot be changed back to 6 clock mode. reset a reset is accomplished by holding the rst pin high for at least two machine cycles (12 oscillator periods in 6 clock mode, or 24 oscillator periods in 12 clock mode), while the oscillator is running. to insure a good power-on reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. at power-on, the voltage on v cc and rst must come up at the same time for a proper start-up. ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above v ih1 (min.) is applied to rst. the value on the ea pin is latched when rst is deasserted and has no further effect.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 11 low power modes stop clock mode the static design enables the clock speed to be reduced down to 0 mhz (stopped). when the oscillator is stopped, the ram and special function registers retain their values. this mode allows step-by-step utilization and reduces system power consumption by lowering the clock frequency down to any value. for lowest power consumption the power-down mode is suggested. idle mode in the idle mode (see table 2), the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode to save even more power, a power-down mode (see table 2) can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power-down is the last instruction executed. the on-chip ram and special function registers retain their values down to 2.0 v and care must be taken to return v cc to the minimum specified operating voltages before the power-down mode is terminated. either a hardware reset or external interrupt can be used to exit from power-down. reset redefines all the sfrs but does not change the on-chip ram. an external interrupt allows both the sfrs and the on-chip ram to retain their values. to properly terminate power-down the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). with an external interrupt, int0 and int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator, but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power-down. power-on flag the power-on flag (pof) is set by on-chip circuitry when the v cc level on the p89c660/662/664/668 rises from 0 to 5 v. the pof bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after power-down. the v cc level must remain above 3 v for the pof to remain unaffected by the v cc level. design consideration when the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, however, access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when the idle mode is terminated by reset, the instruction following the one that invokes the idle mode should not be one that writes to a port pin or to external memory. once ? mode the once (aon-circuit emulationo) mode facilitates testing and debugging of systems without the device having to be removed from the circuit. the once mode is invoked by: 1. pulling ale low while the device is in reset and psen is high; 2. holding ale low as rst is deactivated. while the device is in once mode, the port 0 pins go into a float state, and the other port pins and ale and psen are weakly pulled high. the oscillator circuit remains active. while the device is in this mode, an emulator or test cpu can be used to drive the circuit. normal operation is restored when a normal reset is applied. programmable clock-out a 50% duty cycle clock can be programmed to come out on p1.0. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50% duty cycle clock ranging from 122 hz to 8 mhz at a 16 mhz operating frequency (61 hz to 4 mhz in 12 clock mode). to configure the timer/counter 2 as a clock generator, bit c/t 2 (in t2con) must be cleared and bit t20e in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in this equation: oscillator frequency n (65536 rcap2h, rcap2l) n = 2 in 6 clock mode 4 in 12 clock mode where (rcap2h,rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. in the clock-out mode timer 2 roll-overs will not generate an interrupt. this is similar to when it is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate generator and a clock generator simultaneously. note, however, that the baud-rate and the clock-out frequency will be the same. table 2. external pin status during idle and power-down mode mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 12 i 2 c serial communication e sio1 the i 2 c serial port is identical to the i 2 c serial port on the 8xc554, 8xc654, and 8xc652 devices. note that the p89c660/662/664/668 i 2 c pins are alternate functions to port pins p1.6 and p1.7. because of this, p1.6 and p1.7 on these parts do not have a pull-up structure as found on the 80c51. therefore p1.6 and p1.7 have open drain outputs on the p89c660/662/664/668. the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: bidirectional data transfer between masters and slaves multimaster bus (no central master) arbitration between simultaneously transmitting masters without corruption of serial data on the bus serial clock synchronization allows devices with different bit rates to communicate via one serial bus serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer the i 2 c bus may be used for test and diagnostic purposes the output latches of p1.6 and p1.7 must be set to logic 1 in order to enable sio1. the p89c66x on-chip i 2 c logic provides a serial interface that meets the i 2 c bus specification and supports all transfer modes (other than the low-speed mode) from and to the i 2 c bus. the sio1 logic handles bytes transfer autonomously. it also keeps track of serial transfers, and a status register (s1sta) reflects the status of sio1 and the i 2 c bus. the cpu interfaces to the i 2 c logic via the following four special function registers: s1con (sio1 control register), s1sta (sio1 status register), s1dat (sio1 data register), and s1adr (sio1 slave address register). the sio1 logic interfaces to the external i 2 c bus via two port 1 pins: p1.6/scl (serial clock line) and p1.7/sda (serial data line). a typical i 2 c bus configuration is shown in figure 1. figure 2 shows how a data transfer is accomplished on the bus. depending on the state of the direction bit (r/w), two types of data transfers are possible on the i 2 c bus: 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a anot acknowledgeo is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. modes of operation the on-chip sio1 logic may operate in the following four modes: 1. master transmitter mode: serial data output through p1.7/sda while p1.6/scl outputs the serial clock. the first transmitted byte contains the slave address of the receiving device (7 bits) and the data direction bit. in this mode the data direction bit (r/w ) will be logic 0, and we say that a awo is transmitted. thus the first byte transmitted is sla+w. serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. 2. master receiver mode: the first transmitted byte contains the slave address of the transmitting device (7 bits) and the data direction bit. in this mode the data direction bit (r/w ) will be logic 1, and we say that an aro is transmitted. thus the first byte transmitted is sla+r. serial data is received via p1.7/sda while p1.6/scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are output to indicate the beginning and end of a serial transfer. 3. slave receiver mode: serial data and the serial clock are received through p1.7/sda and p1.6/scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. 4. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted via p1.7/sda while the serial clock is input through p1.6/scl. start and stop conditions are recognized as the beginning and end of a serial transfer. in a given application, sio1 may operate as a master and as a slave. in the slave mode, the sio1 hardware looks for its own slave address and the general call address. if one of these addresses is detected, an interrupt is requested. when the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bus arbitration is lost in the master mode, sio1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 13 v dd other device with i 2 c interface p89c66x other device with i 2 c interface p1.7/sda p1.6/scl sda scl i 2 c bus r p r p su01710 figure 1. typical i 2 c bus configuration scl start condition s sda p/s msb acknowledgment signal from receiver clock line held low while interrupts are serviced 1 2 7 8 9 1 2 38 ack 9 ack repeated if more bytes are transferred acknowledgment signal from receiver slave address r/w direction bit stop condition repeated start condition su00965 figure 2. data transfer on the i 2 c bus sio1 implementation and operation figure 3 shows how the on-chip i 2 c bus interface is implemented, and the following text describes the individual blocks. input filters and output stages the input filters have i 2 c compatible input levels. if the input voltage is less than 1.5 v, the input logic level is interpreted as 0; if the input voltage is greater than 3.0 v, the input logic level is interpreted as 1. input signals are synchronized with the internal clock (f osc /4), and spikes shorter than three oscillator periods are filtered out. the output stages consist of open drain transistors that can sink 3ma at v out < 0.4 v. these open drain outputs do not have clamping diodes to v dd . thus, if the device is connected to the i 2 c bus and v dd is switched off, the i 2 c bus is not affected. address register, s1adr this 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which sio1 will respond when programmed as a slave transmitter or receiver. the lsb (gc) is used to enable general call address (00h) recognition. comparator the comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in s1adr). it also compares the first received 8-bit byte with the general call address (00h). if an equality is found, the appropriate status bits are set and an interrupt is requested. shift register, s1dat this 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been received. data in s1dat is always shifted from right to left; the first bit to be transmitted is the msb (bit 7) and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 14 f osc /4 internal bus address register comparator shift register control register status register arbitration & sync logic timing & control logic serial clock generator ack status decoder timer 1 overflow interrupt 8 8 8 8 s1sta status bits s1con s1dat input filter output stage p1.7 input filter output stage p1.6 p1.6/scl p1.7/sda s1adr su00966 figure 3. i 2 c bus serial interface block diagram
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 15 arbitration and synchronization logic in the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the i 2 c bus. if another device on the bus overrules a logic 1 and pulls the sda line low, arbitration is lost, and sio1 immediately changes from master transmitter to slave receiver. sio1 will continue to output clock pulses (on scl) until transmission of the current serial byte is complete. arbitration may also be lost in the master receiver mode. loss of arbitration in this mode can only occur while sio1 is returning a anot acknowledge: (logic 1) to the bus. arbitration is lost when another device on the bus pulls this signal low. since this can occur only at the end of a serial byte, sio1 generates no further clock pulses. figure 4 shows the arbitration procedure. the synchronization logic will synchronize the serial clock generator with the clock pulses on the scl line from another device. if two or more master devices generate clock pulses, the amarko duration is determined by the device that generates the shortest amarks,o and the aspaceo duration is determined by the device that generates the longest aspaces.o figure 5 shows the synchronization procedure. a slave may stretch the space duration to slow down the bus master. the space duration may also be stretched for handshaking purposes. this can be done after each bit or after a complete byte transfer. sio1 will stretch the scl space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. the serial interrupt flag (si) is set, and the stretching continues until the serial interrupt flag is cleared. ack 1. another device transmits identical serial data. sda 1 234 89 scl (1) (1) (2) (3) 2. another device overrules a logic 1 (dotted line) transmitted by sio1 (master) by pulling the sda line low. arbitration is lost, and sio1 enters the slave receiver mode. 3. sio1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. sio1 will not generate clock pulses for the next byte. data on sda originates from the new master once it has won arbitration. su00967 figure 4. arbitration procedure (1) scl (3) (1) sda mark duration space duration (2) 1. another service pulls the scl line low before the sio1 amarko duration is complete. the serial clock generator is immediately reset and commences with the aspaceo duration by pulling scl low. 2. another device still pulls the scl line low after sio1 releases scl. the serial clock generator is forced into the wait state until the scl line is released. 3. the scl line is released, and the serial clock generator commences with the mark duration. su00968 figure 5. serial clock synchronization
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 16 serial clock generator this programmable clock pulse generator provides the scl clock pulses when sio1 is in the master transmitter or master receiver mode. it is switched off when sio1 is in a slave mode. the programmable output clock frequencies are: f osc /120, f osc /9600 (12-clock mode) or f osc /60, f osc /4800 (6-clock mode) and the timer 1 overflow rate divided by eight. the output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other scl clock sources as described above. timing and control the timing and control logic generates the timing and control signals for serial byte handling. this logic block provides the shift pulses for s1dat, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the i 2 c bus status. control register, s1con this 7-bit special function register is used by the microcontroller to control the following sio1 functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. status decoder and status register the status decoder takes all of the internal status bits and compresses them into a 5-bit code. this code is unique for each i 2 c bus status. the 5-bit code may be used to generate vector addresses for fast processing of the various service routines. each service routine processes a particular bus status. there are 26 possible bus states if all four modes of sio1 are used. the 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. the three least significant bits of the status register are always zero. if the status code is used as a vector to service routines, then the routines are displaced by eight address locations. eight bytes of code is sufficient for most of the service routines. the four sio1 special function registers the microcontroller interfaces to sio1 via four special function registers. these four sfrs (s1adr, s1dat, s1con, and s1sta) are described individually in the following sections. the address register, s1adr the cpu can read from and write to this 8-bit, directly addressable sfr. s1adr is not affected by the sio1 hardware. the contents of this register are irrelevant when sio1 is in a master mode. in the slave modes, the seven most significant bits must be loaded with the microcontroller's own slave address, and, if the least significant bit is set, the general call address (00h) is recognized; otherwise it is ignored. s1adr (dbh) xgc 7 65 432 10 own slave address x xx xx x the most significant bit corresponds to the first bit received from the i 2 c bus after a start condition. a logic 1 in s1adr corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. the data register, s1dat s1dat contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from and write to this 8-bit, directly addressable sfr while it is not in the process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag is set. data in s1dat remains stable as long as si is set. data in s1dat is always shifted from right to left: the first bit to be transmitted is the msb (bit 7), and, after a byte has been received, the first bit of received data is located at the msb of s1dat. while data is being shifted out, data on the bus is simultaneously being shifted in; s1dat always contains the last data byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in s1dat. s1dat (dah) sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 7 65 43 2 1 0 shift direction sd7 - sd0: eight bits to be transmitted or just received. a logic 1 in s1dat corresponds to a high level on the i 2 c bus, and a logic 0 corresponds to a low level on the bus. serial data shifts through s1dat from right to left. figure 6 shows how data in s1dat is serially transferred to and from the sda line. s1dat and the ack flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. the ack flag is controlled by the sio1 hardware and cannot be accessed by the cpu. serial data is shifted through the ack flag into s1dat on the rising edges of serial clock pulses on the scl line. when a byte has been shifted into s1dat, the serial data is available in s1dat, and the acknowledge bit is returned by the control logic during the ninth clock pulse. serial data is shifted out from s1dat via a buffer (bsd7) on the falling edges of clock pulses on the scl line. when the cpu writes to s1dat, bsd7 is loaded with the content of s1dat.7, which is the first bit to be transmitted to the sda line (see figure 7). after nine serial clock pulses, the eight bits in s1dat will have been transmitted to the sda line, and the acknowledge bit will be present in ack. note that the eight transmitted bits are shifted back into s1dat. the control register, s1con the cpu can read from and write to this 8-bit, directly addressable sfr. two bits are affected by the sio1 hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c bus. the sto bit is also cleared when ens1 = a0o. s1con (d8h) ens1 sta sto si aa cr1 cr0 7 6543210 cr2 ens1, the sio1 enable bit: ens1 = a0o: when ens1 is a0o, the sda and scl outputs are in a high impedance state. sda and scl input signals are ignored, sio1 is in the anot addressedo slave state, and the sto bit in s1con is forced to a0o. no other bits are affected. p1.6 and p1.7 may be used as open drain i/o ports. ens1 = a1o: when ens1 is a1o, sio1 is enabled. the p1.6 and p1.7 port latches must be set to logic 1. ens1 should not be used to temporarily release sio1 from the i2c bus since, when ens1 is reset, the i2c bus status is lost. the aa flag should be used instead (see description of the aa flag in the following text).
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 17 internal bus 8 bsd7 s1dat ack scl sda shift pulses su00969 figure 6. serial input/output configuration shift in sda scl d7 d6 d5 d4 d3 d2 d1 d0 a shift ack & s1dat ack (2) (2) (2) (2) (2) (2) (2) (2) a (2) (2) (2) (2) (2) (2) (2) (2) (1) (1) s1dat shift bsd7 bsd7 d7 d6 d5 d4 d3 d2 d1 d0 (3) loaded by the cpu (1) valid data in s1dat (2) shifting data in s1dat and ack (3) high level on sda shift out su00970 figure 7. shift-in and shift-out timing in the following text, it is assumed that ens1 = a1o. the astarto flag, sta: sta = a1o: when the sta bit is set to enter a master mode, the sio1 hardware checks the status of the i2c bus and generates a start condition if the bus is free. if the bus is not free, then sio1 waits for a stop condition (which will free the bus) and generates a start condition after a delay of half a clock period of the internal serial clock generator. if sta is set while sio1 is already in a master mode and one or more bytes are transmitted or received, sio1 transmits a repeated start condition. sta may be set at any time. sta may also be set when sio1 is an addressed slave. sta = a0o: when the sta bit is reset, no start condition or repeated start condition will be generated. the stop flag, sto: sto = a1o: when the sto bit is set while sio1 is in a master mode, a stop condition is transmitted to the i 2 c bus. when the stop condition is detected on the bus, the sio1 hardware clears the sto flag. in a slave mode, the sto flag may be set to recover from an error condition. in this case, no stop condition is transmitted to the i 2 c bus. however, the sio1 hardware behaves as if a stop condition has been received and switches to the defined anot addressedo slave receiver mode. the sto flag is automatically cleared by hardware.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 18 if the sta and sto bits are both set, the a stop condition is transmitted to the i 2 c bus if sio1 is in a master mode (in a slave mode, sio1 generates an internal stop condition which is not transmitted). sio1 then transmits a start condition. sto = a0o: when the sto bit is reset, no stop condition will be generated. the serial interrupt flag, si: si = a1o: when the si flag is set, then, if the ea and es1 (interrupt enable register) bits are also set, a serial interrupt is requested. si is set by hardware when one of 25 of the 26 possible sio1 states is entered. the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. a high level on the scl line is unaffected by the serial interrupt flag. si must be reset by software. si = a0o: when the si flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the scl line. the assert acknowledge flag, aa: aa = a1o: if the aa flag is set, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: the aown slave addresso has been received the general call address has been received while the general call bit (gc) in s1adr is set a data byte has been received while sio1 is in the master receiver mode a data byte has been received while sio1 is in the addressed slave receiver mode aa = a0o: if the aa flag is reset, a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on scl when: a data has been received while sio1 is in the master receiver mode a data byte has been received while sio1 is in the addressed slave receiver mode when sio1 is in the addressed slave transmitter mode, state c8h will be entered after the last serial is transmitted (see figure 11). when si is cleared, sio1 leaves state c8h, enters the not addressed slave receiver mode, and the sda line remains at a high level. in state c8h, the aa flag can be set again for future address recognition. when sio1 is in the not addressed slave mode, its own slave address and the general call address are ignored. consequently, no acknowledge is returned, and a serial interrupt is not requested. thus, sio1 can be temporarily released from the i 2 c bus while the bus status is monitored. while sio1 is released from the bus, start and stop conditions are detected, and serial data is shifted in. address recognition can be resumed at any time by setting the aa flag. if the aa flag is set when the part's own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. the clock rate bits cr0, cr1, and cr2: these three bits determine the serial clock frequency when sio1 is in a master mode. the various serial rates are shown in table 3. a 12.5 khz bit rate may be used by devices that interface to the i 2 c bus via standard i/o port lines which are software driven and slow. 100 khz is usually the maximum bit rate and can be derived from a 16 mhz, 12 mhz, or a 6 mhz oscillator. a variable bit rate (0.5 khz to 62.5 khz) may also be used if timer 1 is not required for any other purpose while sio1 is in a master mode. the frequencies shown in table 3 are unimportant when sio1 is in a slave mode. in the slave modes, sio1 will automatically synchronize with any clock frequency up to 100 khz. the status register, s1sta s1sta is an 8-bit read-only special function register. the three least significant bits are always zero. the five most significant bits contain the status code. there are 26 possible status codes. when s1sta contains f8h, no relevant state information is available and no serial interrupt is requested. all other s1sta values correspond to defined sio1 states. when each of these states is entered, a serial interrupt is requested (si = a1o). a valid status code is present in s1sta one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 19 table 3. serial clock rates 6-clock mode bit frequency (khz) at f osc cr2 cr1 cr0 3 mhz 6 mhz 8 mhz 12 mhz 2 15 mhz 2 f osc divided by 0 0 0 23 47 62.5 94 117 1 128 0 0 1 27 54 71 107 1 134 1 112 0 1 0 31 63 83.3 125 1 156 1 96 0 1 1 37 75 100 150 1 188 1 80 1 0 0 6.25 12.5 17 25 31 480 1 0 1 50 100 133 1 200 1 250 1 60 1 1 0 100 200 267 1 400 1 500 1 30 1 1 1 0.24 < 62.5 0 < 255 0.49 < 62.5 0 < 254 0.65 < 55.6 0 < 253 0.98 < 50.0 0 < 251 1.22 < 52.1 0 < 250 48 (256 (reload value timer 1)) reload value timer 1 in mode 2. 12-clock mode bit frequency (khz) at f osc cr2 cr1 cr0 6 mhz 12 mhz 16 mhz 24 mhz 3 30 mhz 3 f osc divided by 0 0 0 23 47 62.5 94 117 1 256 0 0 1 27 54 71 107 1 134 1 224 0 1 0 31 63 83.3 125 1 156 1 192 0 1 1 37 75 100 150 1 188 1 160 1 0 0 6.25 12.5 17 25 31 960 1 0 1 50 100 133 1 200 1 250 1 120 1 1 0 100 200 267 1 400 1 500 1 60 1 1 1 0.24 < 62.5 0 < 255 0.49 < 62.5 0 < 254 0.65 < 55.6 0 < 253 0.98 < 50.0 0 < 251 1.22 < 52.1 0 < 250 96 (256 (reload value timer 1)) reload value timer 1 in mode 2. notes: 1. these frequencies exceed the upper limit of 100 khz of the i 2 c-bus specification and cannot be used in an i 2 c-bus application. 2. at f osc = 12 mhz/15 mhz the maximum i 2 c bus rate of 100 khz cannot be realized due to the fixed divider rates. 3. at f osc = 24 mhz/30 mhz the maximum i 2 c bus rate of 100 khz cannot be realized due to the fixed divider rates.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 20 more information on sio1 operating modes the four operating modes are: master transmitter master receiver slave receiver slave transmitter data transfers in each mode of operation are shown in figures 8-11. these figures contain the following abbreviations: abbreviation explanation s start condition sla 7-bit slave address r read bit (high level at sda) w write bit (low level at sda) a acknowledge bit (low level at sda) a not acknowledge bit (high level at sda) data 8-bit data byte p stop condition in figures 8-11, circles are used to indicate when the serial interrupt flag is set. the numbers in the circles show the status code held in the s1sta register. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. when a serial interrupt routine is entered, the status code in s1sta is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in tables 4-8. master transmitter mode in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see figure 8). before the master transmitter mode can be entered, s1con must be initialized as follows: s1con (d8h) cr2 ens1 sta sto si aa cr1 cr0 7 6543210 1000x bit rate bit rate cr0, cr1, and cr2 define the serial bit rate. ens1 must be set to logic 1 to enable sio1. if the aa bit is reset, sio1 will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. in other words, if aa is reset, sio0 cannot enter a slave mode. sta, sto, and si must be reset. the master transmitter mode may now be entered by setting the sta bit using the setb instruction. the sio1 logic will now test the i 2 c bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag (si) is set, and the status code in the status register (s1sta) will be 08h. this status code must be used to vector to an interrupt service routine that loads s1dat with the slave address and the data direction bit (sla+w). the si bit in s1con must then be reset before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. there are 18h, 20h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 4. after a repeated start condition (state 10h). sio1 may switch to the master receiver mode by loading s1dat with sla+r). master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 9). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load s1dat with the 7-bit slave address and the data direction bit (sla+r). the si bit in s1con must then be cleared before the serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in s1sta are possible. these are 40h, 48h, or 38h for the master mode and also 68h, 78h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 5. ens1, cr1, and cr0 are not affected by the serial transfer and are not referred to in table 5. after a repeated start condition (state 10h), sio1 may switch to the master transmitter mode by loading s1dat with sla+w. slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 10). to initiate the slave receiver mode, s1adr and s1con must be loaded as follows: s1adr (dbh) xgc 7 65 432 1 0 own slave address x xx xx x the upper 7 bits are the address to which sio1 will respond when addressed by a master. if the lsb (gc) is set, sio1 will respond to the general call address (00h); otherwise it ignores the general call address. s1con (d8h) ens1 sta sto si aa cr1 cr0 7 6543210 x1 0001x x cr2 cr0, cr1, and cr2 do not affect sio1 in the slave mode. ens1 must be set to logic 1 to enable sio1. the aa bit must be set to enable sio1 to acknowledge its own slave address or the general call address. sta, sto, and si must be reset. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be a0o (w) for sio1 to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag (i) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 6. the slave receiver mode may also be entered if arbitration is lost while sio1 is in the master mode (see status 68h and 78h). if the aa bit is reset during a transfer, sio1 will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 21 ???????? ???????? ??? ??? ??? ??? ??? ??? s sla wa a data p ??????? ??????? ??????? s sla w ??? ??? a p ??? ??? ??? a p 08h 18h 28h ??? ??? r 38h a or a other mst continues a or a other mst continues 38h 30h 20h 68h 78h 80h other mst continues a mt 10h to mst/rec mode entry = mr to corresponding states in slave mode successful transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave ???? ???? ???? ???? ??? ??? ??? ?? ?? ?? a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 4. data su00971 figure 8. format and states in the master transmitter mode
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 22 ???????? ???????? ??? ??? s sla ra data p ??????? ??????? ??????? s sla r ??? ??? a p 08h 40h 50h ??? ??? w 38h a or a other mst continues other mst continues 38h 48h 68h 78h 80h other mst continues a mr 10h to mst/trx mode entry = mt to corresponding states in slave mode successful reception from a slave transmitter next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or acknowledge bit arbitration lost and addressed as slave ???? ???? ???? ???? ???? n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 5. ??? ??? a ???? ???? data ??? ??? a 58h ??? ??? ??? a ?? ?? data a su00972 figure 9. format and states in the master receiver mode
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 23 ??????? ??????? ??? ??? ???? ???? ??? ??? s sla wa a data p or s a 60h 80h 68h reception of the own slave address and one or more data bytes all are acknowledged. last data byte received is not acknowledged arbitration lost as mst and addressed as slave reception of the general call address and one or more data bytes last data byte is not acknowledged arbitration lost as mst and addressed as slave by general call ???? ???? ???? ???? ??? ??? ??? ?? ?? ?? a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 6. data a sla ??? ??? data 80h a0h ??? ??? ??? a 88h p or s ????? ????? ????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ??? general call aa data p or s 70h 90h 78h a data 90h a0h a 98h p or s a su00973 figure 10. format and states in the slave receiver mode
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 24 ???????? ???????? ???????? ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? s sla ra data p or s b0h a8h b8h reception of the own slave address and transmission of one or more data bytes a data a c0h ???? ???? ?? ?? n any number of data bytes and their associated acknowledge bits this number (contained in s1sta) corresponds to a defined state of the i 2 c bus. see table 7. data a ??? ??? ??? all a1os ??? ??? ??? a a ???? ???? from master to slave from slave to master c8h p or s last data byte transmitted. switched to not addressed slave (aa bit in s1con = a0o arbitration lost as mst and addressed as slave su00974 figure 11. format and states of the slave transmitter mode
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 25 table 4. master transmitter mode status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa 08h a start condition has been transmitted load sla+w x 0 0 x sla+w will be transmitted; ack bit will be received 10h a repeated start diti h b load sla+w or x 0 0 x as above condition has been transmitted load sla+r x 0 0 x sla+w will be transmitted; sio1 will be switched to mst/rec mode 18h sla+w has been transmitted; ack has bid load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received been received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 20h sla+w has been transmitted; not ack hb id load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received has been received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 28h data byte in s1dat has been transmitted; ack hb id load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received has been received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 30h data byte in s1dat has been transmitted; not ack h b i d load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received ack has been received no s1dat action or 1 0 0 x repeated start will be transmitted; no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 38h arbitration lost in sla+r/w or db no s1dat action or 0 0 0 x i 2 c bus will be released; not addressed slave will be entered data bytes no s1dat action 1 0 0 x a start condition will be transmitted when the bus becomes free
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 26 table 5. master receiver mode status status of the i 2 c application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa 08h a start condition has been transmitted load sla+r x 0 0 x sla+r will be transmitted; ack bit will be received 10h a repeated start diti h b load sla+r or x 0 0 x as above condition has been transmitted load sla+w x 0 0 x sla+w will be transmitted; sio1 will be switched to mst/trx mode 38h arbitration lost in not ack bit no s1dat action or 0 0 0 x i 2 c bus will be released; sio1 will enter a slave mode no s1dat action 1 0 0 x a start condition will be transmitted when the bus becomes free 40h sla+r has been transmitted; ack has bid no s1dat action or 0 0 0 0 data byte will be received; not ack bit will be returned been received no s1dat action 0 0 0 1 data byte will be received; ack bit will be returned 48h sla+r has been t itt d not ack no s1dat action or 1 0 0 x repeated start condition will be transmitted transmitted; not ack has been received no s1dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no s1dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 50h data byte has been received; ack has been d read data byte or 0 0 0 0 data byte will be received; not ack bit will be returned returned read data byte 0 0 0 1 data byte will be received; ack bit will be returned 58h data byte has been i d not ack h read data byte or 1 0 0 x repeated start condition will be transmitted received; not ack has been returned read data byte or 0 1 0 x stop condition will be transmitted; sto flag will be reset read data byte 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 27 table 6. slave receiver mode status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa 60h own sla+w has been received; ack hb d no s1dat action or x 0 0 0 data byte will be received and not ack will be returned has been returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 68h arbitration lost in sla+r/w as master; own sla+w has b i d ack no s1dat action or x 0 0 0 data byte will be received and not ack will be returned been received, ack returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 70h general call address (00h) has been received ; ack has no s1dat action or x 0 0 0 data byte will be received and not ack will be returned received ack has been returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 78h arbitration lost in sla+r/w as master; general call address has been received no s1dat action or x 0 0 0 data byte will be received and not ack will be returned has been received , ack has been returned no s1dat action x 0 0 1 data byte will be received and ack will be returned 80h previously addressed with own slv address; data has b i d ack read data byte or x 0 0 0 data byte will be received and not ack will be returned been received; ack has been returned read data byte x 0 0 1 data byte will be received and ack will be returned 88h previously addressed with own sla; data bhb read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address byte has been received; not ack has been returned read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. 90h previously addressed with general call; data byte has been i d ack h read data byte or x 0 0 0 data byte will be received and not ack will be returned received; ack has been returned read data byte x 0 0 1 data byte will be received and ack will be returned 98h previously addressed with general call; data b h b read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address data byte has been received; not ack has been returned read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 28 table 6. slave receiver mode (continued) status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa a0h a stop condition or repeated start di i h b no stdat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address condition has been received while still addressed as slv/rec or slv/trx no stdat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 slv/rec or slv/trx no stdat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free no stdat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. table 7. slave transmitter mode status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa a8h own sla+r has been received; ack hb d load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received has been returned load data byte x 0 0 1 data byte will be transmitted; ack will be received b0h arbitration lost in sla+r/w as master; own sla+r has load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received been received, ack has been returned load data byte x 0 0 1 data byte will be transmitted; ack bit will be received b8h data byte in s1dat has been transmitted; ack has been load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received ack has been received load data byte x 0 0 1 data byte will be transmitted; ack bit will be received c0h data byte in s1dat has been transmitted; not ack h b no s1dat action or 0 0 0 01 switched to not addressed slv mode; no recognition of own sla or general call address not ack has been received no s1dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 no s1dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free no s1dat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free. c8h last data byte in s1dat has been i d (aa 0) no s1dat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address transmitted (aa = 0); ack has been received no s1dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1 no s1dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free no s1dat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if s1adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 29 table 8. miscellaneous states status status of the application software response status code (s1sta) status of the i 2 c bus and sio1 hardware to/from s1dat to s1con next action taken by sio1 hardware (s1sta) sio1 hardware to/from s1dat sta sto si aa f8h no relevant state information available; si = 0 no s1dat action no s1con action wait or proceed current transfer 00h bus error during mst or selected slave modes, due to an illegal start or stop condition. state 00h can also occur when interference causes sio1 to enter an undefined state. no s1dat action 0 1 0 x only the internal hardware is affected in the mst or addressed slv modes. in all cases, the bus is released and sio1 is switched to the not addressed slv mode. sto is reset. slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 11). data transfer is initialized as in the slave receiver mode. when s1adr and s1con have been initialized, sio1 waits until it is addressed by its own slave address followed by the data direction bit which must be a1o (r) for sio1 to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from s1sta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 7. the slave transmitter mode may also be entered if arbitration is lost while sio1 is in the master mode (see state b0h). if the aa bit is reset during a transfer, sio1 will transmit the last byte of the transfer and enter state c0h or c8h. sio1 is switched to the anot addressedo slave mode and will ignore the master receiver if it continues the transfer. thus the master receiver receives all 1s as serial data. while aa is reset, sio1 does not respond to its own slave address or a general call address. however, the i 2 c bus is still monitored, and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio1 from the i 2 c bus. miscellaneous states there are two s1sta codes that do not correspond to a defined sio1 hardware state (see table 8). these are discussed below. s1sta = f8h this status code indicates that no relevant information is available because the serial interrupt flag, si, is not yet set. this occurs between other states and when sio1 is not involved in a serial transfer. s1sta = 00h this status code indicates that a bus error has occurred during an sio1 serial transfer. a bus error is caused when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interference disturbs the internal sio1 signals. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this causes sio1 to enter the anot addressedo slave mode (a defined state) and to clear the sto flag (no other bits in s1con are affected). the sda and scl lines are released (a stop condition is not transmitted). some special cases the sio1 hardware has facilities to handle the following special cases that may occur during a serial transfer. simultaneous repeated start conditions from two masters a repeated start condition may be generated in the master transmitter or master receiver modes. a special case occurs if another master simultaneously generates a repeated start condition (see figure 12). until this occurs, arbitration is not lost by either master since they were both transmitting the same data. if the sio1 hardware detects a repeated start condition on the i 2 c bus before generating a repeated start condition itself, it will release the bus, and no interrupt request is generated. if another master frees the bus by generating a stop condition, sio1 will transmit a normal start condition (state 08h), and a retry of the total serial data transfer can commence. data transfer after loss of arbitration arbitration may be lost in the master transmitter and master receiver modes (see figure 4). loss of arbitration is indicated by the following states in s1sta: 38h, 68h, 78h, and b0h (see figures 8 and 9). if the sta flag in s1con is set by the routines which service these states, then, if the bus is free again, a start condition (state 08h) is transmitted without intervention by the cpu, and a retry of the total serial transfer can commence. forced access to the i 2 c bus in some applications, it may be possible for an uncontrolled source to cause a bus hang-up. in such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between sda and scl. if an uncontrolled source generates a superfluous start or masks a stop condition, then the i 2 c bus stays busy indefinitely. if the sta flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the i 2 c bus is possible. this is achieved by setting the sto flag while the sta flag is still set. no stop condition is transmitted. the sio1 hardware behaves as if a stop condition was received and is able to transmit a start condition. the st0 flag is cleared by hardware (see figure 13).
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 30 s 08h sla w a data a s both masters continue with sla transmission 18h 28h other master sends repeated start condition earlier su00975 figure 12. simultaneous repeated start conditions from 2 masters sta flag time out sda line scl line start condition su00976 figure 13. forced access to a busy i 2 c bus i 2 c bus obstructed by a low level on scl or sda an i 2 c bus hang-up occurs if sda or scl is pulled low by an uncontrolled source. if the scl line is obstructed (pulled low) by a device on the bus, no further serial transfer is possible, and the sio1 hardware cannot resolve this type of problem. when this occurs, the problem must be resolved by the device that is pulling the scl bus line low. if the sda line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the scl line (see figure 14). the sio1 hardware transmits additional clock pulses when the sta flag is set, but no start condition can be generated because the sda line is pulled low while the i 2 c bus is considered free. the sio1 hardware attempts to generate a start condition after every two additional clock pulses on the scl line. when the sda line is eventually released, a normal start condition is transmitted, state 08h is entered, and the serial transfer continues. if a forced bus access occurs or a repeated start condition is transmitted while sda is obstructed (pulled low), the sio1 hardware performs the same action as described above. in each case, state 08h is entered after a successful start condition is transmitted and normal serial transfer continues. note that the cpu is not involved in solving these bus hang-up problems. bus error a bus error occurs when a start or stop condition is present at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data, or an acknowledge bit. the sio1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. when a bus error is detected, sio1 immediately switches to the anot addressedo slave mode, releases the sda and scl lines, sets the interrupt flag, and loads the status register with 00h. this status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in table 8.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 31 sta flag start condition (1) unsuccessful attempt to send a start condition (2) sda line released (3) successful attempt to send a start condition; state 08h is entered sda line scl line (1) (1) (2) (3) su00977 figure 14. recovering from a bus obstruction caused by a low level on sda an i 2 c byte-oriented system driver is described in application note an435. please visit http://www.semiconductors.philips.com/products/all_appnotes.html
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 32 timer 0 and timer 1 operation timer 0 and timer 1 the atimero or acountero function is selected by control bits c/t in the special function register tmod (see figure 15). these two timer/counters have four operating modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. mode 0 putting either timer into mode 0 makes it behave as an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 16 shows the mode 0 operation. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfn. the counted input is enabled to the timer when trn = 1 and either gate = 0 or intn = 1. trn is a control bit in the special function register tcon (figure 17). (setting gate = 1 allows the timer to be controlled by external input intn , to facilitate pulse width measurements). the 13-bit register consists of all 8 bits of thn and the lower 5 bits of tln. the upper 3 bits of tln are indeterminate and should be ignored. setting the run flag (trn) does not clear the registers. mode 0 operation is the same for timer 0 as for timer 1. there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). mode 1 mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. mode 2 mode 2 configures the timer register as an 8-bit counter (tln) with automatic reload, as shown in figure 18. overflow from tln not only sets tfn, but also reloads tln with the contents of thn, which is preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer 0 as for timer 1. mode 3 timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in figure 19. tl0 uses the timer 0 control bits: c/t , gate, tr0, and tf0 as well as pin int0 . th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the atimer 1o interrupt. mode 3 is provided for applications requiring an extra 8-bit timer on the counter. putting timer 0 in mode 3 allows an 80c51 to have three timer/counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. gate c/t m1 m0 gate c/t m1 m0 bit symbol function tmod.3/ gate gating control when set. timer/counter ano is enabled only while aintn o pin is high and tmod.7 atrno control pin is set. when cleared timer ano is enabled whenever atrno control bit is set. tmod.2/ c/t timer or counter selector cleared for timer operation (input from internal system clock.) tmod.6 set for counter operation (input from atno input pin). m1 m0 operating 0 0 8048 timer: atlno serves as 5-bit prescaler. 0 1 16-bit timer/counter: athno and atlno are cascaded; there is no prescaler. 1 0 8-bit auto-reload timer/counter: athno holds a value which is to be reloaded into atlno each time it overflows. 1 1 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. 1 1 (timer 1) timer/counter 1 stopped. su01580 timer 1 timer 0 not bit addressable tmod address = 89h reset value = 00h 76543 2 1 0 figure 15. timer/counter 0/1 mode control (tmod) register
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 33 intn pin timer n gate bit trn tln (5 bits) thn (8 bits) tfn interrupt control c/t = 0 c/t = 1 su01618 osc d* tn pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode. figure 16. timer/counter 0/1 mode 0: 13-bit timer/counter it0 bit symbol function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. tcon.6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. tcon.4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. tcon.3 ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. tcon.1 ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. su01516 ie0 it1 ie1 tr0 tf0 tr1 tf1 bit addressable tcon address = 88h reset value = 00h 76543210 figure 17. timer/counter 0/1 control (tcon) register
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 34 tln (8 bits) tfn interrupt control c/t = 0 c/t = 1 thn (8 bits) reload intn pin timer n gate bit trn su01619 osc d* tn pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode. figure 18. timer/counter 0/1 mode 2: 8-bit auto-reload tl0 (8 bits) tf0 interrupt control th0 (8 bits) tf1 interrupt control tr1 int0 pin timer 0 gate bit tr0 su01620 c/t = 0 c/t = 1 *d = 6 in 6-clock mode; d = 12 in 12-clock mode. osc d* osc d* t0 pin figure 19. timer/counter 0 mode 3: two 8-bit counters
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 35 timer 2 operation timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by c/t 2 in the special function register t2con (see figure 20). timer 2 has three operating modes: capture mode auto-reload mode (up or down counting) baud rate generator mode (see table 10) capture mode in the capture mode there are two options which are selected by bit exen2 in t2con. if exen2 = 0, then timer 2 is a 16-bit timer or counter (as selected by c/t 2 in t2con) which, upon overflowing sets bit tf2, the timer 2 overflow bit. this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ie register). if exen2 = 1, timer 2 operates as described above, with the added feature that a 1-to-0 transition at external input pin t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h. in addition, the transition at t2ex causes bit exf2 in t2con to be set. if timer 2 interrupt has been enabled, exf2 will generate an interrupt (which vectors to the same location as timer 2 overflow interrupt). the timer 2 interrupt service routine can interrogate tf2 and exf2 to determine which event caused the interrupt. the capture mode is illustrated in figure 21 (there is no reload value for tl2 and th2 in this mode). even when a capture event occurs from t2ex, the counter keeps on counting t2ex pin transitions or osc/6 pulses (osc/12 in 12 clock mode). auto-reload mode (up or down counter) in the 16-bit auto-reload mode, timer 2 can be configured as either a timer or counter (c/t 2 in t2con), then programmed to count up or down. the counting direction is determined by bit dcen (down counter enable) which is located in the t2mod register (see figure 22). when reset is applied (dcen = 0), timer 2 defaults to counting up. if dcen bit is set, timer 2 can count up or down depending on the value of the t2ex pin. figure 23 shows timer 2 which will count up automatically since dcen = 0. in this mode there are two options selected by bit exen2 in t2con register. if exen2 = 0, then timer 2 counts up to 0ffffh and sets the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h are preset by software. if exen2 = 1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input pin t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 are 1. in figure 24 dcen = 1 which enables timer 2 to count up or down. this mode allows pin t2ex to control the direction of count. when a logic 1 is applied at pin t2ex timer 2 will count up. timer 2 will overflow at 0ffffh and set the tf2 flag, which can then generate an interrupt, if the interrupt is enabled. this timer overflow also causes the 16-bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. when a logic 0 is applied at pin t2ex this causes timer 2 to count down. the timer will underflow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. timer 2 underflow sets the tf2 flag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. the external flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution if needed. the exf2 flag does not generate an interrupt in this mode of operation. (msb) (lsb) symbol position name and significance tf2 t2con.7 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1. exf2 t2con.6 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk t2con.5 receive clock flag. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk t2con.4 transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 t2con.3 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 start/stop control for timer 2. a logic 1 starts the timer. c/t 2 t2con.1 timer or counter select. (timer 2) 0 = internal timer (osc/6 in 6-clock mode or osc/12 in 12-clock mode) 1 = external event counter (falling edge triggered). cp/rl 2 t2con.0 capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. tf2 exf2 rclk tclk exen2 tr2 c/t 2 cp/rl 2 su01251 figure 20. timer/counter 2 (t2con) control register
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 36 table 9. timer 2 operating modes rclk + tclk cp/rl 2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 baud rate generator x x 0 (off) osc n* c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin capture su01252 * n = 6 in 6-clock mode, or 12 in 12-clock mode. figure 21. timer 2 in capture mode not bit addressable symbol function e not implemented, reserved for future use.* t2oe timer 2 output enable bit. dcen down count enable bit. when set, this allows timer 2 to be configured as an up/down counter depending on the value of the t2ex pin. e e e e e e t2oe dcen su01714 76543210 * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reser ved bit is indeterminate. bit t2mod address = 0c9h reset value = xxxx xx00b figure 22. timer 2 mode (t2mod) control register
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 37 osc n* c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload su01253 * n = 6 in 6-clock mode, or 12 in 12-clock mode. figure 23. timer 2 in auto-reload mode (dcen = 0) n* c/t 2 = 0 c/t 2 = 1 tl2 th2 tr2 control t2 pin su01254 ffh ffh rcap2l rcap2h (up counting reload value) t2ex pin tf2 interrupt count direction 1 = up 0 = down exf2 overflow (down counting reload value) toggle osc * n = 6 in 6-clock mode, or 12 in 12-clock mode. figure 24. timer 2 auto reload mode (dcen = 1)
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 38 osc c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8-bits) th2 (8-bits) 16 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload 2 a0o a1o rx clock 16 tx clock a0o a1o a0o a1o timer 1 overflow note availability of additional external interrupt. smod rclk tclk su01213 figure 25. timer 2 in baud rate generator mode table 10. timer 2 commonly used generated baud rates baud rate timer 2 12 clock mode 6 clock mode osc freq rcap2h rcap2l 375 k 750 k 12 mhz ff ff 9.6 k 19.2 k 12 mhz ff d9 2.8 k 5.6 k 12 mhz ff b2 2.4 k 4.8 k 12 mhz ff 64 1.2 k 2.4 k 12 mhz fe c8 300 600 12 mhz fb 1e 110 220 12 mhz f2 af 300 600 6 mhz fd 8f 110 220 6 mhz f9 57 baud rate generator mode bits tclk and/or rclk in t2con (see figure 20) allow the serial port transmit and receive baud rates to be derived from either timer 1 or timer 2. when tclk = 0, timer 1 is used as the serial port transmit baud rate generator. when tclk = 1, timer 2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port receive baud rate. with these two bits, the serial port can have different receive and transmit baud rates one generated by timer 1, the other by timer 2. table 10 shows commonly used baud rates and how they can be obtained from timer 2. figure 25 shows timer 2 in baud rate generation mode. the baud rate generation mode is similar to the auto-reload mode, in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2's overflow rate given below: modes 1 and 3 baud rates timer 2 overflow rate 16 the timer can be configured for either atimero or acountero operation. in many applications, it is configured for atimero operation (c/t 2 = 0). timer operation is different for timer 2 when it is being used as a baud rate generator. usually, as a timer, it would increment every machine cycle (i.e., 1 / 6 the oscillator frequency in 6 clock mode, 1 / 12 the oscillator frequency in 12 clock mode). as a baud rate generator, it increments at the oscillator frequency in 6 clock mode (f osc /2 in 12 clock mode). thus the baud rate formula is as follows: oscillator frequency [n* [65536 (rcap2h, rcap2l)]] modes 1 and 3 baud rates = * n = 16 in 6 clock mode 32 in 12 clock mode where: (rcap2h, rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. the timer 2 as a baud rate generator mode shown in figure 25, is valid only if rclk and/or tclk = 1 in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable flag) is set, a 1-to-0 transition in t2ex (timer/counter 2 trigger input) will set exf2 (t2 external flag) but will not cause a reload from (rcap2h, rcap2l) to (th2,tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 39 when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. as a baud rate generator, timer 2 is incremented every state time (f osc /2) or asynchronously from pin t2; under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload, and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing timer 2 or rcap2 registers. summary of baud rate equations: timer 2 is in baud rate generating mode. if timer 2 is being clocked through pin t2(p1.0) the baud rate is: baud rate timer 2 overflow rate 16 if timer 2 is being clocked internally, the baud rate is: baud rate f osc [n* [65536 (rcap2h, rcap2l)]] * n = 16 in 6 clock mode 32 in 12 clock mode where f osc = oscillator frequency to obtain the reload value for rcap2h and rcap2l, the above equation can be rewritten as: rcap2h, rcap2l 65536 f osc n* baud rate timer/counter 2 set-up except for the baud rate generator mode, the values given for t2con do not include the setting of the tr2 bit. therefore, bit tr2 must be set, separately, to turn the timer on. see table 11 for set-up of timer 2 as a timer. also see table 12 for set-up of timer 2 as a counter. table 11. timer 2 as a timer t2con mode internal control (note 1) external control (note 2) 16-bit auto-reload 00h 08h 16-bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h table 12. timer 2 as a counter tmod mode internal control (note 1) external control (note 2) 16-bit 02h 0ah auto-reload 03h 0bh notes: 1. capture/reload occurs only on timer/counter overflow. 2. capture/reload occurs on timer/counter overflow and a 1-to-0 transition on t2ex (p1.1) pin except when timer 2 is used in the baud rate generator mode.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 40 full-duplex enhanced uart standard uart operation a full-duplex serial port can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 the oscillator frequency in 12-clock mode or 1/6 the oscillator frequency in 6-clock mode. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in 12-clock mode or 1/16 or 1/32 the oscillator frequency in 6-clock mode. mode 3: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9th bit goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren't being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0. in mode 1, it can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. serial port control register the serial port control and status register is the special function register scon, shown in figure 26. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). baud rates the baud rate in mode 0 is fixed: mode 0 baud rate = oscillator frequency / 12 (12-clock mode) or / 6 (6-clock mode). the baud rate in mode 2 depends on the value of bit smod in special function register pcon. if smod = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency. if smod = 1, the baud rate is 1/32 the oscillator frequency. in 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively. mode 2 baud rate = 2 smod n (oscillator frequency) where: n = 64 in 12-clock mode, 32 in 6-clock mode the baud rates in modes 1 and 3 are determined by the timer 1 or timer 2 overflow rate. using timer 1 to generate baud rates when timer 1 is used as the baud rate generator (t2con.5 = 0, t2con.4 = 0), the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: mode 1, 3 baud rate = 2 smod n (timer 1 overflow rate) where: n = 32 in 12-clock mode, 16 in 6-clock mode the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either atimero or acountero operation, and in any of its 3 running modes. in the most typical applications, it is configured for atimero operation, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1, 3 baud rate = 2 smod n oscillator frequency 12 [256(th1)] where: n = 32 in 12-clock mode, 16 in 6-clock mode one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. figure 27 lists various commonly used baud rates and how they can be obtained from timer 1.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 41 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then rl will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if a valid stop bit was no t received. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2=0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the o ther modes, in any serial transmission. must be cleared by software. ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the o ther modes, in any serial reception (except see sm2). must be cleared by software. sm0 sm1 sm2 ren tb8 rb8 ti ri where sm0, sm1 specify the serial port mode, as follows: sm0 sm1 mode description baud rate 0 0 0 shift register f osc /12 (12-clock mode) or f osc /6 (6-clock mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 (12-clock mode) or f osc /32 or f osc /16 (6-clock mode) 1 1 3 9-bit uart variable su01626 bit addressable scon address = 98h reset value = 00h 76543 210 figure 26. serial port control (scon) register baud rate f smod timer 1 mode 12-clock mode 6-clock mode f osc smod c/t mode reload value mode 0 max 1.67 mhz 3.34 mhz 20 mhz x x x x mode 2 max 625 k 1250 k 20 mhz 1 x x x mode 1, 3 max 104.2 k 208.4 k 20 mhz 1 0 2 ffh mode 1, 3 19.2 k 38.4 k 11.059 mhz 1 0 2 fdh 9.6 k 19.2 k 11.059 mhz 0 0 2 fdh 4.8 k 9.6 k 11.059 mhz 0 0 2 fah 2.4 k 4.8 k 11.059 mhz 0 0 2 f4h 1.2 k 2.4 k 11.059 mhz 0 0 2 e8h 137.5 275 11.986 mhz 0 0 2 1dh 110 220 6 mhz 0 0 2 72h 110 220 12 mhz 0 0 1 feebh figure 27. timer 1 generated commonly used baud rates more about mode 0 serial data enters and exits through rxd. txd outputs the shift clock. eight data bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 the oscillator frequency (12-clock mode) or 1/6 the oscillator frequency (6-clock mode). figure 28 shows a simplified functional diagram of the serial port in mode 0, and associated timing. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal at s6p2 also loads a 1 into the 9th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between awrite to sbufo and activation of send. send enables the output of the shift register to the alternate output function line of p3.0 and also enable shift clock to the alternate output function line of p3.1. shift clock is low during s3, s4, and s5 of every machine cycle, and high during s6, s1, and s2. at s6p2 of every machine cycle in which send is active, the contents of the transmit shift are shifted to the right one position. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control block to do one last shift and then deactivate send and set t1. both of these actions occur at s1p1 of the 10th machine cycle after awrite to sbuf.o reception is initiated by the condition ren = 1 and r1 = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 to the receive shift register, and activates receive in the next clock phase. receive enable shift clock to the alternate output function line of p3.1. shift clock makes transitions at s3p1 and s6p1 of every machine cycle. at s6p2 of every machine cycle in which receive is active, the contents of the receive shift register are
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 42 shifted to the left by one position. the value that comes in, from the right, is the value that was sampled at the p3.0 pin at s5p2 of the same machine cycle. as data bits come in from the right, 1s shift out to the left. when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle, after the write to scon that cleared ri, receive is cleared as ri is set. more about mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the 80c51 the baud rate is determined by the timer 1 or timer 2 overflow rate. figure 29 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit receive. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads a 1 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left. when the msb of the data byte is at the output position of the shift register, the 1 that was initially loaded into the 9th position is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 10th divide-by-16 rollover after awrite to sbuf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. r1 = 0, and 2. either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. at this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in rxd. more about modes 2 and 3 eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8) can be assigned the value of 0 or 1. on receive, the 9th data bit goes into rb8 in scon. the baud rate is programmable to either 1/32 or 1/64 (12-clock mode), or 1/16 or 1/32 (6-clock mode) of the oscillator frequency in mode 2. mode 3 may have a variable baud rate generated from timer 1 or timer 2. figures 30 and 31 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads tb8 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal). the transmission begins with activation of send, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. thereafter, only zeros are clocked in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 11th divide-by-16 rollover after awrite to sbuf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. ri = 0, and 2. either sm2 = 0, or the received 9th data bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the first 8 data bits go into sbuf. one bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the rxd input.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 43 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send shift start s6 rx control start shift receive rx clock t1 r1 serial port interrupt 1 1 1 1 1 1 1 0 input shift register ren ri load sbuf shift shift clock rxd p3.0 alt output function txd p3.1 alt output function sbuf read sbuf 80c51 internal bus rxd p3.0 alt input function write to sbuf s6p2 send shift rxd (data out) d0 d1 d2 d3 d4 d5 d6 d7 transmit txd (shift clock) ti s3p1 s6p1 write to scon (clear ri) ri receive shift rxd (data in) d0 d1 d2 d3 d4 d5 d6 txd (shift clock) s5p2 receive d7 ale s4 . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 su00539 lsb lsb msb msb figure 28. serial port mode 0
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 44 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start rx clock ri t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 timer 1 overflow smod = 1 smod = 0 shift bit detector transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rxd rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data 16 load sbuf shift 1ffh su00540 figure 29. serial port mode 1
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 45 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start load sbuf rx clock t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 smod = 1 smod = 0 shift bit detector rxd stop bit gen. mode 2 phase 2 clock (1/2 f osc ) r1 16 shift 1ffh transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data (smod is pcon.7) tb8 rb8 stop bit gen. su00541 figure 30. serial port mode 2
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 46 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start rx clock t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 timer 1 overflow smod = 1 smod = 0 shift bit detector rxd r1 16 load sbuf shift 1ffh transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data tb8 rb8 stop bit gen. su00542 figure 31. serial port mode 3
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 47 enhanced uart in addition to the standard operation, the uart can perform framing error detect by looking for missing stop bits, and automatic address recognition. the uart also fully supports multiprocessor communication as does the standard 80c51 uart. when used for framing error detect, the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the s0con register. the fe bit shares the s0con.7 bit with sm0, and the function of s0con.7 is determined by pcon.6 (smod0) (see figure 32). if smod0 is set then s0con.7 functions as fe. s0con.7 functions as sm0 when smod0 is cleared. when used as fe, s0con.7 can only be cleared by software (refer to figure 33). automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in s0con. in the 9-bit uart modes (mode 2 and mode 3), the receive interrupt flag (ri) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 34. the 8-bit mode is called mode 1. in this mode, the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits, and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 is ignored. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are adon't careo. the saden mask can be logically anded with the saddr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are trended as don't-cares. in most cases, interpreting the don't-cares as ones, the broadcast address will be ff hexadecimal. upon reset, saddr (sfr address 0a9h) and saden (sfr address 0b9h) are leaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard 80c51 type uart drivers which do not make use of this feature.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 48 s0con address = 98h reset value = 0000 0000b sm0/fe sm1 sm2 ren tb8 rb8 tl rl bit addressable (smod0 = 0/1)* symbol function fe framing error bit. this bit is set by the receiver when an invalid stop bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the smod0 bit must be set to enable access to the fe bit. sm0 serial port mode bit 0, (smod0 must = 0 to access bit sm0) sm1 serial port mode bit 1 sm0 sm1 mode description baud rate** 0 0 0 shift register f osc /6 (6 clock mode) or f osc /12 (12 clock mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32 or f osc /16 (6 clock mode) or f osc /64 or f osc /32 (12 clock mode) 1 1 3 9-bit uart variable sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then rl will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then rl will not be activated unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. tl transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. rl receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. note: *smod0 is located at pcon6. **f osc = oscillator frequency su01451 bit: 76543210 figure 32. s0con: serial port control register
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 49 smod1 smod0 pof lvf gf0 gf1 idl pcon (87h) sm0 / fe sm1 sm2 ren tb8 rb8 ti ri s0con (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit set fe bit if stop bit is 0 (framing error) sm0 to uart mode control 0 : s0con.7 = sm0 1 : s0con.7 = fe su01452 figure 33. uart framing error detection sm0 sm1 sm2 ren tb8 rb8 ti ri s0con (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren=1, rb8=1 and areceived addresso = aprogrammed addresso when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address. su01453 figure 34. uart multiprocessor communication, automatic address recognition
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 50 interrupt priority structure the p89c660/662/664/668 has an 8 source four-level interrupt structure (see table 13). there are 4 sfrs associated with the four-level interrupt. they are the ie, ip, ien1, and iph (see figures 35, 36, 37, and 38). the iph (interrupt priority high) register makes the four-level interrupt structure possible. the iph is located at sfr address b7h. the structure of the iph register and a description of its bits is shown in figure 37. the function of the iph sfr, when combined with the ip sfr, determines the priority of each interrupt. the priority of each interrupt is determined as shown in the following table: priority bits interrupt priority level iph.x ip.x interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) the priority scheme for servicing the interrupts is the same as that for the 80c51, except that there are four interrupt levels rather than two (as on the 80c51). an interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. if an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. if a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. when the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. table 13. interrupt table source polling priority request bits hardware clear? vector address x0 1 ie0 n (l) 1 y (t) 2 03h si01 (i 2 c) 2 e n 2bh t0 3 tp0 y 0bh x1 4 ie1 n (l) y (t) 13h t1 5 tf1 y 1bh sp 6 ri, ti n 23h t2 7 tf2, exf2 n 3bh pca 8 cf, ccfn n = 04 n 33h notes: 1. l = level activated 2. t = transition activated ex0 ien0 (0a8h) enable bit = 1 enables the interrupt. enable bit = 0 disables it. bit symbol function ien0.7 ea global disable bit. if ea = 0, all interrupts are disabled. if ea = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. ien0.6 ec pca interrupt enable bit ien0.5 es1 i 2 c interrupt enable bit. ien0.4 es0 serial port interrupt enable bit. ien0.3 et1 timer 1 interrupt enable bit. ien0.2 ex1 external interrupt 1 enable bit. ien0.1 et0 timer 0 interrupt enable bit. ien0.0 ex0 external interrupt 0 enable bit. su01454 et0 ex1 et1 es0 es1 ec ea 0 1 2 3 4 5 6 7 figure 35. ie registers
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 51 px0 ip (0b8h) priority bit = 1 assigns high priority priority bit = 0 assigns low priority bit symbol function ip.7 pt2 timer 2 interrupt priority bit. ip.6 ppc pca interrupt priority bit ip.5 ps1 serial i/o1 (i 2 c) interrupt priority bit. ip.4 ps0 serial port interrupt priority bit. ip.3 pt1 timer 1 interrupt priority bit. ip.2 px1 external interrupt 1 priority bit. ip.1 pt0 timer 0 interrupt priority bit. ip.0 px0 external interrupt 0 priority bit. su01455 pt0 px1 pt1 ps0 ps1 ppc pt2 0 1 2 3 4 5 6 7 figure 36. ip registers px0h iph (b7h) priority bit = 1 assigns higher priority priority bit = 0 assigns lower priority bit symbol function iph.7 pt2h timer 2 interrupt priority bit high. iph.6 ppch pca interrupt priority bit iph.5 ps1h serial i/o (i 2 c) interrupt priority bit high. iph.4 ps0h serial port interrupt priority bit high. iph.3 pt1h timer 1 interrupt priority bit high. iph.2 px1h external interrupt 1 priority bit high. iph.1 pt0h timer 0 interrupt priority bit high. iph.0 px0h external interrupt 0 priority bit high. su01456 pt0h px1h pt1h ps0h ps1h ppch pt2h 0 1 2 3 4 5 6 7 figure 37. iph registers et2 ien1 (e8h) enable bit = 1 enables the interrupt enable bit = 0 disables the interrupt bit symbol function ien1.7 e ien1.6 e ien1.5 e ien1.4 e ien1.3 e ien1.2 e ien1.1 e ien1.0 et2 timer 2 interrupt enable bit. su01095 e e e e e e e 0 1 2 3 4 5 6 7 figure 38. ien1 registers
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 52 reduced emi mode the ao bit (auxr.0) in the auxr register when set disables the ale output. reduced emi mode auxr (8eh) 765432 1 0 extram ao auxr.1 extram (see more detailed description in auxr.0 ao figure 53.) dual dptr the dual dptr structure (see figure 39) is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps (auxr1.0), that allows the program code to switch between them. ? new register name: auxr1# ? sfr address: a2h ? reset value: xxxxx0x0b auxr1 (a2h) 76 5 43210 enboot gf2 0 dps where: dps (auxr1.0), enables switching between dptr0 and dptr1. select reg dps dptr0 0 dptr1 1 the dps bit status should be saved by software when switching between dptr0 and dptr1. the gf2 bit is a general purpose user-defined flag. note that bit 2 is not writable and is always read as a zero. this allows the dps bit to be quickly toggled simply by executing an inc auxr1 instruction without affecting the gf2 bit. the enboot bit determines whether the bootrom is enabled or disabled. this bit will automatically be set if the status byte is non zero during reset or psen is pulled low, ale floats high, and ea > v ih on the falling edge of reset. otherwise, this bit will be cleared during reset. dps dptr1 dptr0 dph (83h) dpl (82h) external data memory su00745a bit0 auxr1 figure 39. dptr instructions the instructions, that refer to dptr, refer to the data pointer that is currently selected by the dps bit (auxr1.0). the six instructions that use the dptr are as follows: inc dptr increments the data pointer by 1 mov dptr, #data16 loads the dptr with a 16-bit constant mov a, @ a+dptr move code byte relative to dptr to acc movx a, @ dptr move external ram (16-bit address) to acc movx @ dptr , a move acc to external ram (16-bit address) jmp @ a + dptr jump indirect relative to dptr the data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the sfrs. see application note an458 for more details.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 53 programmable counter array (pca) the programmable counter array available on the 89c66x is a special 16-bit timer that has five 16-bit capture/compare modules associated with it. each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. each module has a pin associated with it in port 1. module 0 is connected to p1.3(cex0), module 1 to p1.4(cex1), etc. the basic pca configuration is shown in figure 40. the pca timer is a common time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency, the timer 0 overflow, or the input on the eci pin (p1.2). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr as follows (see figure 43): cps1 cps0 pca timer count source 0 0 1/6 oscillator frequency (6 clock mode); 1/12 oscillator frequency (12 clock mode) 0 1 1/2 oscillator frequency (6 clock mode); 1/4 oscillator frequency (12 clock mode) 1 0 timer 0 overflow 1 1 external input at eci pin in the cmod sfr, there are three additional bits associated with the pca. they are cidl which allows the pca to stop during idle mode, wdte which enables or disables the watchdog function on module 4, and ecf which, when set, causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. these functions are shown in figure 41. the watchdog timer function is implemented in module 4 (see figure 50). the ccon sfr contains the run control bit for the pca, and the flags for the pca timer (cf) and each module (refer to figure 44). to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing this bit. the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set, the cf bit can only be cleared by software. bits 0 through 4 of the ccon register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. the pca interrupt system is shown in figure 42. each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see figure 45). the registers contain the bits that control the mode that each module will operate in. the eccf bit (ccapmn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2), when set, causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapmn.3), when set, will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set, both edges will be enabled and a capture will occur for either transition. the last bit ecom (ccapmn.6), when set, enables the comparator function. figure 46 shows the ccapmn settings for the various pca functions. there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output. module functions: 16-bit capture 16-bit timer 16-bit high speed output 8-bit pwm watchdog timer (module 4 only) module 0 module 1 module 2 module 3 module 4 p1.3/cex0 p1.4/cex1 p1.5/cex2 p3.4/cex3 p3.5/cex4 16 bits pca timer/counter time base for pca modules 16 bits su01416 figure 40. programmable counter array (pca)
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 54 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (c0h) ch cl overflow interrupt 16bit up counter idle to pca modules cmod (c1h) cidl wdte cps1 cps0 ecf osc/6 (6 clock mode) or osc/12 (12 clock mode) timer 0 overflow external input (p1.2/eci) decode 00 01 10 11 su01256 osc/2 (6 clock mode) or osc/4 (12 clock mode) figure 41. pca timer/counter module 0 module 1 module 2 module 3 module 4 pca timer/counter cf cr ccf4 ccf3 ccf2 ccf1 ccf0 cmod.0 ecf ccapmn.0 eccfn to interrupt priority decoder ccon (c0h) ie.6 ec ie.7 ea su01097 figure 42. pca interrupt system
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 55 cmod address = c1h reset value = 00xx x000b cidl wdte cps1 cps0 ecf bit: symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. not implemented, reserved for future use.* cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 selected pca input** 0 0 0 internal clock, f osc /6 in 6 clock mode (f osc /12 in 12 clock mode) 0 1 1 internal clock, f osc /2 in 6 clock mode (f osc /4 in 12 clock mode) 1 0 2 timer 0 overflow 1 1 3 external clock at eci/p1.2 pin (max. rate = f osc /4 in 6 clock mode, f ocs /8 in 12 clock mode) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function of cf. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ** f osc = oscillator frequency su01257 76543210 figure 43. cmod: pca counter mode register ccon address = 0c0h reset value = 00x0 0000b cf cr ccf4 ccf3 ccf2 ccf1 ccf0 bit addressable bit: symbol function cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. not implemented, reserved for future use*. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01099 76543210 figure 44. ccon: pca counter control register
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 56 ccapmn address ccapm0 0c2h ccapm1 0c3h ccapm2 0c4h ccapm3 0c5h ccapm4 0c6h reset value = x000 0000b ecomn cappn capnn matn togn pwmn eccfn not bit addressable bit: symbol function not implemented, reserved for future use*. ecomn enable comparator. ecomn = 1 enables the comparator function. cappn capture positive, cappn = 1 enables positive edge capture. capnn capture negative, capnn = 1 enables negative edge capture. matn match. when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle. when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. note: *user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01100 76543210 figure 45. ccapmn: pca modules compare/capture registers ecomn cappn capnn matn togn pwmn eccfn module function x 0 0 0 0 0 0 0 no operation x x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cexn x x 0 1 0 0 0 x 16-bit capture by a negative trigger on cexn x x 1 1 0 0 0 x 16-bit capture by a transition on cexn x 1 0 0 1 0 0 x 16-bit software timer x 1 0 0 1 1 0 x 16-bit high speed output x 1 0 0 0 0 1 0 8-bit pwm x 1 0 0 1 x 0 x watchdog timer figure 46. pca module modes (ccapmn register) pca capture mode to use one of the pca modules in the capture mode, either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs, the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set, then an interrupt will be generated (refer to figure 47). 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture registers, and when a match occurs, an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 48). high speed output mode in this mode, the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode, the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 49). pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 50 shows the pwm function. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable by using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln sfr, the output will be low. when it is equal to or greater than, the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. this allows pwm update without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 57 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (0c0h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (c2h c6h) ch cl ccapnh ccapnl cexn capture pca interrupt pca timer/counter 0 000 (to ccfn) su01101 figure 47. pca capture mode match cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (c0h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (c2h c6h) ch cl ccapnh ccapnl pca interrupt pca timer/counter 00 00 16bit comparator (to ccfn) enable write to ccapnh reset write to ccapnl 01 su01102 figure 48. pca compare mode
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 58 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (c0h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (c2h c6h) ch cl ccapnh ccapnl pca interrupt pca timer/counter 10 00 16bit comparator (to ccfn) write to ccapnh reset write to ccapnl 01 enable cexn toggle match su01103 figure 49. pca high speed output mode cl < ccapnl ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (c2h c6h) pca timer/counter 00 00 cl ccapnl cexn 8bit comparator overflow ccapnh enable 0 1 cl >= ccapnl 0 su01104 figure 50. pca pwm mode
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 59 ecomn cappn capnn matn togn pwmn eccfn ccapm4 (c6h) ch cl ccap4h ccap4l reset pca timer/counter x0 00 16bit comparator match enable write to ccap4l reset write to ccap4h 10 1 cmod (c1h) cidl wdte cps1 cps0 ecf x su01105 module 4 figure 51. pca watchdog timer m(module 4 only) pca watchdog timer an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 51 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer, 2. periodically change the pca timer value so it will never match the compare values, or 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it. the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most applications the first solution is the best option. figure 52 shows the code for initializing the watchdog timer. module 4 can be configured in either compare mode, and the wdte bit in cmod must also be set. the user's software must periodically change (ccap4h,ccap4l) to keep a match from occurring with the pca timer (ch,cl). this code is given in the watchdog routine in figure 52. this routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. thus, the purpose of the watchdog would be defeated. instead, call this subroutine from the main program within 2 16 count of the pca timer.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 60 init_watchdog: mov ccapm4, #4ch ; module 4 in compare mode mov ccap4l, #0ffh ; write to low byte first mov ccap4h, #0ffh ; before pca timer counts up to ; ffff hex, these compare values ; must be changed orl cmod, #40h ; set the wdte bit to enable the ; watchdog timer without changing ; the other bits in cmod ; ;******************************************************************** ; ; main program goes here, but call watchdog periodically. ; ;******************************************************************** ; watchdog: clr ea ; hold off interrupts mov ccap4l, #00 ; next compare value is within mov ccap4h, ch ; 255 counts of the current pca setb ea ; timer value ret figure 52. pca watchdog timer initialization code
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 61 expanded data ram addressing the p89c660/662/664/668 has internal data memory that is mapped into four separate segments: the lower 128 bytes of ram, upper 128 bytes of ram, 128 bytes special function register (sfr), and 256 bytes expanded ram (eram) (256 bytes for the '660; 768 bytes for the '662; 1792 bytes for the '664; 7936 bytes for the '668). the four segments are: 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. 3. the special function registers, sfrs, (addresses 80h to ffh) are directly addressable only. 4. the 256/768/1792/7936-bytes expanded ram (eram, 00h xffh/2ffh/6ffh/1fffh) are indirectly accessed by move external instruction, movx, and with the extram bit cleared, see figure 53. the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically separate from sfr space. when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram, or to sfr space by the addressing mode used in the instruction. instructions that use direct addressing, access sfr space. for example: mov 0a0h,a accesses the sfr at location 0a0h (which is p2). instructions that use indirect addressing, access the upper 128 bytes of data ram. for example: mov @r0,a where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). the eram can be accessed by indirect addressing, with extram bit cleared and movx instructions. this part of memory is physically located on-chip, logically occupies the first 256 bytes (660), 768 (662), 1792 (664), 7936 (668) of external data memory. with extram = 0, the eram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to eram will not affect ports p0, p3.6 (wr#) and p3.7 (rd#). p2 sfr is in output state during external addressing. for example, with extram = 0, movx @r0,a where r0 contains 0a0h, access the eram at address 0a0h rather than external memory. an access to external data memory locations higher than the eram will be performed with the movx dptr instructions in the same way as in the standard 80c51 (with p0 and p2 as data/address bus, and p3.6 and p3.7 as write and read timing signals. refer to figure 54). with extram = 1, movx @ri and movx @dptr will be similar to the standard 80c51. movx @ ri will provide an 8-bit address multiplexed with data on port 0 and any output port pins can be used to output higher order address bits. this is to provide the external paging capability. movx @dptr will generate a 16-bit address. port 2 outputs the high-order eight address bits (the contents of dph) while port 0 multiplexes the low-order eight address bits (the contents of dpl) with data. movx @ri and movx @dptr will generate either read or write signals on p3.6 (wr ) and p3.7 (rd ). the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack may not be located in the eram. auxr reset value = xxxx xx10b e eeeee extram ao not bit addressable bit: symbol function ao disable/enable ale ao operating mode 0 ale is emitted at a constant rate of 1 / 3 the oscillator frequency (6 clock mode; 1 / 6 f osc in 12 clock mode) 1 ale is active only during off-chip memory access. extram internal/external ram access using movx @ri/@dptr extram operating mode 0 internal eram access using movx @ri/@dptr 1 external data memory access. e not implemented, reserved for future use*. note: *user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su01711 76543210 address = 8eh figure 53. auxr: auxiliary register
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 62 eram 256, 768, 1792 or 7936 bytes upper 128 bytes internal ram lower 128 bytes internal ram special function register 000 ff 00 ff 00 80 80 external data memory ffff 0000 su01712 ff/2ff/6ff/1fff figure 54. internal and external data memory address space with extram = 0 hardware watchdog timer (one-time enabled with reset-out for p89c660/662/664/668) the wdt is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is disabled at reset. to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst (sfr location 0a6h). when wdt is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when wdt overflows, it will drive an output reset high pulse at the rst pin. using the wdt to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst (sfr location 0a6h). when wdt is enabled, the user needs to service it by writing 01eh and 0e1h to wdtrst to avoid wdt overflow. the 14-bit counter overflows when it reaches 16383 (3fffh) and this will reset the device. when wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycles. to reset the wdt, the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or written. when the wdt overflows, it will generate an output reset pulse at the rst pin. the reset pulse duration is 98 t osc (6 clock mode; 196 in 12 clock mode), where t osc = 1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 63 flash eprom memory general description the p89c660/662/664/668 flash memory augments eprom functionality with in-circuit electrical erasure and programming. the flash can be read and written as bytes. the chip erase operation will erase the entire program memory. the block erase function can erase any flash byte block. in-system programming and standard parallel programming are both available. on-chip erase and write timing generation contribute to a user-friendly programming interface. the p89c660/662/664/668 flash reliably stores memory contents even after 10,000 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations, produces reliable cycling. the p89c660/662/664/668 uses a +5 v v pp supply to perform the program/erase algorithms. features in-system programming (isp) and in-application programming (iap) ? flash eprom internal program memory with block erase. ? internal 1 kbyte fixed boot rom, containing low-level in-system programming routines and a default serial loader. user program can call these routines to perform in-application programming (iap). the boot rom can be turned off to provide access to the full 64 kbyte of flash memory. ? boot vector allows user provided flash loader code to reside anywhere in the flash memory space. this configuration provides flexibility to the user. ? default loader in boot rom allows programming via the serial port without the need for a user provided loader. ? up to 64 kbytes of external program memory if the internal program memory is disabled (ea = 0). ? programming and erase voltage +5 v (+12 v tolerant). ? read/programming/erase using isp/iap: byte programming (20 s). typical quick erase times: block erase (8 kbytes or 16 kbytes) in 10 seconds. full erase (64 kbytes) in 20 seconds. ? in-system programming. ? programmable security for the code in the flash. ? 10,000 minimum erase/program cycles for each byte. ? 10-year minimum data retention. capabilities of the philips 89c51 flash-based microcontrollers flash organization the p89c660/662/664/668 contains 16kb/32kb/64kb of flash program memory. this memory is organized as 5 separate blocks. the first two blocks are 8 kbytes in size, filling the program memory space from address 0 through 3fff hex. the final three blocks are 16 kbytes in size and occupy addresses from 4000 through ffff hex. figure 55 depicts the flash memory configurations. flash programming and erasure there are three methods of erasing or programming of the flash memory that may be used. first, the flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the boot rom. the end-user application, though, must be executing code from a different block than the block that is being erased or programmed. second, the on-chip isp boot loader may be invoked. this isp boot loader will, in turn, call low-level routines through the same common entry point in the boot rom that can be used by the end-user application. third, the flash may be programmed or erased using the parallel method by using a commercially available eprom programmer. the parallel programming method used by these devices is similar to that used by eprom 87c51, but it is not identical, and the commercially available programmer will need to have support for these devices. boot rom when the microcontroller programs its own flash memory, all of the low level details are handled by code that is permanently contained in a 1 kbyte aboot romo that is separate from the flash memory. a user program simply calls the common entry point with appropriate parameters in the boot rom to accomplish the desired operation. boot rom operations include things like: erase block, program byte, verify byte, program security lock bit, etc. the boot rom overlays the program memory space at the top of the address space from fc00 to ffff hex, when it is enabled. the boot rom may be turned off so that the upper 1 kbytes of flash program memory are accessible for execution.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 64 ffff c000 8000 4000 2000 0000 block 4 16 kbytes block 3 16 kbytes block 2 16 kbytes block 1 8 kbytes block 0 8 kbytes program address boot rom (1 kbyte) ffff fc00 su01264 89c664/89c668 89c662 89c660 figure 55. flash memory configurations power-on reset code execution the p89c660/662/664/668 contains two special flash registers: the boot vector and the status byte. at the falling edge of reset, the p89c660/662/664/668 examines the contents of the status byte. if the status byte is set to zero, power-up execution starts at location 0000h, which is the normal start address of the user's application code. when the status byte is set to a value other than zero, the contents of the boot vector is used as the high byte of the execution address and the low byte is set to 00h. the factory default setting is 0fch, corresponds to the address 0fc00h for the factory masked-rom isp boot loader. a custom boot loader can be written with the boot vector set to the custom boot loader. note: when erasing the status byte or boot vector, both bytes are erased at the same time. it is necessary to reprogram the boot vector after erasing and updating the status byte. hardware activation of the boot loader the boot loader can also be executed by holding psen low, p2.7, p2.6 high, ea greater than v ih (such as +5 v), and ale high (or not connected) at the falling edge of reset. this is the same effect as having a non-zero status byte. this allows an application to be built that will normally execute the end user's code but can be manually forced into isp operation. if the factory default setting for the boot vector (0fch) is changed, it will no longer point to the isp masked-rom boot loader code. if this happens, the only possible way to change the contents of the boot vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the boot vector and status byte. after programming the flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000h.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 65 + 5v (+12v tolerant) +5v txd rxd v ss v pp v cc txd rxd rst xtal2 xtal1 su01265 v ss v cc 89c660 89c662 89c664 89c668 a1o p2.6, p2.7 figure 56. in-system programming with a minimum of pins in-system programming (isp) the in-system programming (isp) is performed without removing the microcontroller from the system. the in-system programming (isp) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the p89c660/662/664/668 through the serial port. this firmware is provided by philips and embedded within each p89c660/662/664/668 device. the philips in-system programming (isp) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses five pins: txd, rxd, v ss , v cc , and v pp (see figure 56). only a small connector needs to be available to interface your application to an external circuit in order to use this feature. the v pp supply should be adequately decoupled and v pp not allowed to exceed datasheet limits. free isp software is available on the philips web site: awinispo 1. direct your browser to the following page: http://www.semiconductors.philips.com/products/standard/ microcontrollers/download/80c51/flash/ 2. download awinisp.exeo 3. execute winisp.exe to install the software free isp software is also available from the embedded systems academy: aflashmagico 1. direct your browser to the following page: http://www.esacademy.com/software/flashmagic/ 2. download flashmagic 3. execute aflashmagic.exeo to install the software using the in-system programming (isp) the isp feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. it is also adaptable to a wide range of oscillator frequencies. this is accomplished by measuring the bit-time of a single bit in a received character. this information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. the isp feature requires that an initial character (an uppercase u) be sent to the p89c660/662/664/668 to establish the baud rate. the isp firmware provides auto-echo of received characters. once baud rate initialization has been performed, the isp firmware will only accept intel hex-type records. intel hex records consist of ascii characters used to represent hexadecimal values and are summarized below: :nnaaaarrdd..ddcc in the intel hex record, the anno represents the number of data bytes in the record. the p89c660/662/664/668 will accept up to 16 (10h) data bytes. the aaaaao string represents the address of the first byte in the record. if there are zero bytes in the record, this field is often set to 0000. the arro string indicates the record type. a record type of a00o is a data record. a record type of a01o indicates the end-of-file mark. in this application, additional record types will be added to indicate either commands or data for the isp facility. the maximum number of data bytes in a record is limited to 16 (decimal). isp commands are summarized in table 14. as a record is received by the p89c660/662/664/668, the information in the record is stored internally and a checksum calculation is performed. the operation indicated by the record type is not performed until the entire record has been received. should an error occur in the checksum, the p89c660/662/664/668 will send an axo out the serial port indicating a checksum error. if the checksum calculation is found to match the checksum in the record, then the command will be executed. in most cases, successful reception of the record will be indicated by transmitting a a.o character out the serial port (displaying the contents of the internal program memory is an exceptions). in the case of a data record (record type 00), an additional check is made. a a.o character will not be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully programmed. for a data record, an axo indicates that the checksum failed to match, and an aro indicates that one of the bytes did not properly program. it is necessary to send a type 02 record (specify oscillator frequency) to the p89c660/662/664/668 before programming data.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 66 the isp facility was designed so that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses. the user thus needs to provide the p89c660/662/664/668 with information required to generate the proper timing. record type 02 is provided for this purpose. table 14. intel-hex records used by in-system programming record type command/data function 00 program data :nnaaaa00dd....ddcc where: nn = number of bytes (hex) in record aaaa = memory address of first byte in record dd....dd = data bytes cc = checksum example: :10008000af5f67f0602703e0322cfa92007780c3fd 01 end of file (eof), no operation :xxxxxx01cc where: xxxxxx = required field, but value is a adon't careo cc = checksum example: :00000001ff 02 specify oscillator frequency :01xxxx02ddcc where: xxxx = required field, but value is a adon't careo dd = integer oscillator frequency rounded down to nearest mhz cc = checksum example: :0100000210ed (dd = 10h = 16, used for 16.016.9 mhz)
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 67 record type command/data function 03 miscellaneous write functions :nnxxxx03ffssddcc where: nn = number of bytes (hex) in record xxxx = required field, but value is a adon't careo 03 = write function ff = subfunction code ss = selection code dd = data input (as needed) cc = checksum subfunction code = 01 (erase blocks) ff = 01 ss = block code as shown below: block 0, 0k to 8k, 00h block 1, 8k to 16k, 20h block 2, 16k to 32k, 40h block 3, 32k to 48k, 80h block 4, 48k to 64k, c0h example: :0200000301c03c erase block 4 subfunction code = 04 (erase boot vector and status byte) ff = 04 ss = don't care example: :020000030400f7 erase boot vector and status byte subfunction code = 05 (program security bits) ff = 05 ss = 00 program security bit 1 (inhibit writing to flash) 01 program security bit 2 (inhibit flash verify) 02 program security bit 3 (disable external memory) example: :020000030501f5 program security bit 2 subfunction code = 06 (program status byte or boot vector) ff = 06 ss = 00 program status byte 01 program boot vector example: :030000030601fcf7 program boot vector with 0fch subfunction code = 07 (full chip erase) erases all blocks, security bits, and sets status and boot vector to default values ff = 07 ss = don't care dd = don't care example: :0100000307f5 full chip erase 04 display device data or blank check record type 04 causes the contents of the entire flash array to be sent out the serial port in a formatted display. this display consists of an address and the contents of 16 bytes starting with that address. no display of the device contents will occur if security bit 2 has been programmed. data to the serial port is initiated by the reception of any character and terminated by the reception of any character. general format of function 04 :05xxxx04sssseeeeffcc where: 05 = number of bytes (hex) in record xxxx = required field, but value is a adon't careo 04 = adisplay device data or blank checko function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check cc = checksum example: :0500000440004fff0069 display 40004fff
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 68 record type command/data function 05 miscellaneous read functions general format of function 05 :02xxxx05ffsscc where: 02 = number of bytes (hex) in record xxxx = required field, but value is a adon't careo 05 = amiscellaneous reado function code ffss = subfunction and selection code 0000 = read signature byte manufacturer id (15h) 0001 = read signature byte device id # 1 (c2h) 0002 = read signature byte device id # 2 0700 = read security bits 0701 = read status byte 0702 = read boot vector cc = checksum example: :020000050001f8 read signature byte device id # 1 06 direct load of baud rate general format of function 06 :02xxxx06hhllcc where: 02 = number of bytes (hex) in record xxxx = required field, but value is a adon't careo 06 = odirect load of baud rateo function code hh = high byte of timer 2 ll = low byte of timer 2 cc = checksum example: :02000006f500f3
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 69 in application programming method several in application programming (iap) calls are available for use by an application program to permit selective erasing and programming of flash sectors. all calls are made through a common interface, pgm_mtp. the programming functions are selected by setting up the microcontroller's registers before making a call to pgm_mtp at fff0h. the oscillator frequency is an integer number rounded down to the nearest megahertz. for example, set r0 to 11 for 11.0592 mhz. results are returned in the registers. the iap calls are shown in table 15. using the watchdog timer (wdt) the 89c66x devices support the use of the wdt in iap. the user specifies that the wdt is to be fed by setting the most significant bit of the function parameter passed in r1 prior to calling pgm_mtp. the wdt function is only supported for block erase when using the quick block erase. the quick block erase is specified by performing a block erase with register r0 = 0. requesting a wdt feed during iap should only be performed in applications that use the wdt since the process of feeding the wdt will start the wdt if the wdt was not working. table 15. iap calls iap call parameter program data byte input parameters: r0 = osc freq (integer) r1 = 02h r1 = 82h (wdt feed, rx2 & 66x only) dptr = address of byte to program acc = byte to program return parameter acc = 00 if pass, !00 if fail sample routine: ;***** program device data (ddata) ***** ;***** acc holds data to write ;***** dptr holds address of byte to write ***** ;***** returns with acc = 00h if successful, else acc neq 00h wrdata: mov auxr1,#20h ;set the enboot bit mov r0, #11 ;fosc mov r1,#02h ;program data function mov a,mydata ;data to write mov dptr,address ;specify address of byte to read call pgm_mtp ;execute the function ret erase block input parameters: r0 = osc freq (integer) r0 = 0 (quick erase, rx2 & 66x only) r1 = 01h r1 = 81h (wdt feed, rx2 & 66x only; can only be used with quick erase) dph = block code as shown below: block 0, 0k to 8k, 00h block 1, 8k to 16k, 20h block 2, 16k to 32k, 40h block 3, 32k to 48k, 80h block 4, 48k to 64k, c0h dpl = 00h return parameter none sample routine: ;***** erase code memory block ***** ;***** dph (7:5) indicates which of the 5 blocks to erase ;***** dptr values for the blocks are: ; 0000h = block 0 ; 2000h = block 1 ; 4000h = block 2 ; 8000h = block 3 ; c000h = block 4 ersblk: mov auxr1,#20h ;set the enboot bit mov r0, #11 ;fosc mov r1,#01h ;erase block mov dptr,#blk_num ;specify which block call pgm_mtp ;execute the function ret
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 70 iap call parameter erase boot vector & status byte input parameters: r0 = osc freq (integer) r1 = 04h r1 = 84h (wdt feed, rx2 & 66x only) dph = 00h dpl = don't care return parameter none sample routine: ;***** erase boot vector (bv) & status byte (sb) ***** ;***** note: this command erases both the sb & bv ersbbv; mov auxr1,#20h ;set the enboot bit mov r0, #11 ;fosc mov r1,#04h ;erase status byte & boot vector mov dph,#00h ;we don't care about dpl call pgm_mtp ;execute the function ret program security bit input parameters: r0 = osc freq (integer) r1 = 05h r1 = 85h (wdt feed, rx2 & 66x only) dph = 00h dpl = 00h security bit # 1 (inhibit writing to flash) 01h security bit # 2 (inhibit flash verify) 02h security bit # 3 (disable external memory) return parameter none sample routines: ;***** program security bit1 ***** ;***** dptr indicates security bit to program ***** wrsb1: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#05h ;program security bit function mov dptr,#0000h ;specify security bit 1 call pgm_mtp ;execute the function ret ;***** program security bit2 ***** ;***** dptr indicates security bit to program ***** wrsb2: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#05h ;program security bit function mov dptr,#0001h ;specify security bit 2 call pgm_mtp ;execute the function ret ;***** program security bit3 ***** ;***** dptr indicates security bit to program ***** wrsb3: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#05h ;program security bit function mov dptr,#0002h ;specify security bit 3 call pgm_mtp ;execute the function ret
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 71 iap call parameter program status byte input parameters: r0 = osc freq (integer) r1 = 06h r1 = 86h (wdt feed, rx2, 66x only) dph = 00h dpl = 00h program status byte acc = status byte return parameter acc = 00 if pass; not 00 if fails sample routine: ;***** program status byte (sb) ***** ;***** dptr indicates program status byte ***** ;***** acc holds new value of status byte to program ***** wrsb: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#06h ;program status byte or boot vector mov dptr,#0000h ;specify status byte mov a,new_sb ; call pgm_mtp ;execute the function ret program boot vector input parameters: r0 = osc freq (integer) r1 = 06h r1 = 86h (wdt feed, rx2 & 66x only) dph = 00h dpl = 01h program boot vector acc = boot vector return parameter acc = 00 if pass; not 00 if fails sample routine: ;***** program boot vector (bv) ***** ;***** dptr indicates program boot vector ***** ;***** acc holds new value of boot vector to program ***** wrbv: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#06h ;program status byte or boot vector mov dptr,#0001h ;specify boot vector mov a,new_sb ;new value for the boot vector call pgm_mtp ;execute the function ret read device data input parameters: r1 = 03h r1 = 83h (wdt feed, rx2 & 66x only) dptr = address of byte to read return parameter acc = value of byte read sample routine: ;*****reads the device data (ddata) ***** ;***** ddata returned in acc ***** ;***** dptr holds address of byte to read ***** rddata: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#03h ;read data function mov dptr,address ;specify address of byte to read call pgm_mtp ;execute the function ret
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 72 iap call parameter read manufacturer id input parameters: r0 = osc freq (integer) r1 = 00h r1 = 80h (wdt feed, rx2 & 66x only) dph = 00h dpl = 00h (manufacturer id) return parameter acc = value of byte read sample routine: ;*****reads the manufacturer id (mid) ***** ;***** mid returned in acc (should be 15h for philips) rdmid: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#00h ;read misc function mov dptr,#0000h ;specify mid call pgm_mtp ;execute the function ret read device id # 1 input parameters: r0 = osc freq (integer) r1 = 00h r1 = 80h (wdt feed, rx2 & 66x only) dph = 00h dpl = 01h (device id # 1) return parameter acc = value of byte read sample routine: ;*****reads the device id 1 (did1) ***** ;***** did1 returned in acc rddid1: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#00h ;read misc function mov dptr,#0001h ;specify device id 1 call pgm_mtp ;execute the function ret read device id # 2 input parameters: r0 = osc freq (integer) r1 = 00h r1 = 80h (wdt feed, rx2 & 66x only) dph = 00h dpl = 02h (device id # 2) return parameter acc = value of byte read sample routine: ;*****reads the device id 2 (did2) ***** ;***** did2 returned in acc rddid2: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#00h ;read misc function mov dptr,#0002h ;specify device id 2 call pgm_mtp ;execute the function ret
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 73 iap call parameter read security bits input parameters: r0 = osc freq (integer) r1 = 07h r1 = 87h (wdt feed, rx2 & 66x only) dph = 00h dpl = 00h (security bits) return parameter acc = value of byte read sample routine: ;*****reads the security bits (sbits) ***** ;***** sbits returned in acc (2:0) rdsbits: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#07h ;read misc function mov dptr,#0000h ;specify security bits call pgm_mtp ;execute the function ret read status byte input parameters: r0 = osc freq (integer) r1 = 07h r1 = 87h (wdt feed, rx2 & 66x only) dph = 00h dpl = 01h (status byte) return parameter acc = value of byte read sample routine: ;*****reads the status byte (sb) ***** ;***** sb returned in acc rdsb: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#07h ;read misc function mov dptr,#0001h ;specify status byte call pgm_mtp ;execute the function ret read boot vector input parameters: r0 = osc freq (integer) r1 = 07h r1 = 87h (wdt feed, rx2 & 66x only) dph = 00h dpl = 02h (boot vector) return parameter acc = value of byte read sample routine: ;*****reads the boot vector (bv) ***** ;***** bv returned in acc rdbv: mov auxr1,#20h ;set the enboot bit mov r0,#11 ;fosc mov r1,#07h ;read misc function mov dptr,#0002h ;specify boot vector call pgm_mtp ;execute the function ret
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 74 security the security feature protects against software piracy and prevents the contents of the flash from being read. the security lock bits are located in flash. the p89c660/662/664/668 has 3 programmable security lock bits that will provide different levels of protection for th e on-chip code and data (see table 16). table 16. security lock bits 1 protection description level lb1 lb2 lb3 protection description 1 0 0 0 movc instructions executed from external program memory are disabled from fetching code bytes from internal memory. 2 1 0 0 same as level 1, plus block erase is disabled. erase or programming of the status byte or boot vector is disabled. 3 1 1 0 same as level 2, plus verify of code memory is disabled. 4 1 1 1 same as level 3, plus external execution is disabled. note: 1. security bits are independent of each other. full-chip erase may be performed regardless of the state of the security bits. 2. any other combination of lockbits is undefined. 3. setting lbx doesn't prevent programming of unprogrammed bits.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 75 absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 0 to +70 or 40 to +85 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 0.5 to +6.5 v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 76 dc electrical characteristics t amb = 0 c to +70 c, 5 v 10% or 40 c to +85 c; 5v 5%; v ss = 0 v symbol parameter test limits unit symbol parameter conditions min typ 1 max unit v il input low voltage 4.5 v < v cc < 5.5 v 0.5 0.2 v cc 0.1 v v il2 input low voltage to p1.6/scl, p1.7/sda 11 0.5 0.3v dd v v ih input high voltage (ports 0, 1, 2, 3, ea ) 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 0.7v cc v cc +0.5 v v ih2 input high voltage, p1.6/scl, p1.7/sda 11 0.7v dd 6.0 v v ol output low voltage, ports 1, 2, 3 8 v cc = 4.5 v i ol = 1.6 ma 2 0.4 v v ol1 output low voltage, port 0, ale, psen 7, 8 v cc = 4.5 v i ol = 3.2 ma 2 0.45 v v ol2 output low voltage, p1.6/scl, p1.7/sda i ol = 3.0 ma 0.4 v v oh output high voltage, ports 1, 2, 3 3 v cc = 4.5 v i oh = 30 m a v cc 0.7 v v oh1 output high voltage (port 0 in external bus mode), ale 9 , psen 3 v cc = 4.5 v i oh = 3.2 ma v cc 0.7 v i il logical 0 input current, ports 1, 2, 3 v in = 0.4 v 1 75 m a i tl logical 1-to-0 transition current, ports 1, 2, 3 6 v in = 2.0 v see note 4 650 m a i li input leakage current, port 0 0.45 < v in < v cc 0.3 10 m a i l2 input leakage current, p1.6/scl, p1.7/sda 0v < vi < 6 v 0v < v dd < 5.5 v 10 m a i cc power supply current (see figure 64): see note 5 active mode (see note 5) idle mode (see note 5) power-down mode or clock stopped (see figure 71 f diti ) t amb = 0 c to 70 c 20 100 m a for conditions) t amb = 40 c to +85 c 125 m a programming and erase mode f osc = 20 mhz 60 ma r rst internal reset pull-down resistor 40 225 k w c io pin capacitance 10 (except ea ) 15 pf notes: 1. typical ratings are not guaranteed. the values listed are at room temperature, 5 v. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus oper ations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v cc 0.7 specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curren t reaches its maximum value when v in is approximately 2 v. 5. see figures 68 through 71 for i cc test conditions and figure 64 for i cc vs freq. active mode: i cc(max) = (2.8 freq. + 8.0)ma for all devices, in 6 clock mode; (1.4 freq. + 8.0)ma in 12 clock mode. idle mode: i cc(max) = (1.2 freq. +1.0)ma in 6 clock mode; (0.6 freq. +1.0)ma in 12 clock mode. 6. this value applies to t amb = 0 c to +70 c. 7. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15 ma (*note: this is 85 c specification.) maximum i ol per 8-bit port: 26 ma maximum total i ol for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. ale is tested to v oh1 , except when ale is off then v oh is the voltage specification. 10. pin capacitance is characterized but not tested. pin capacitance is less than 25 pf. pin capacitance of ceramic package is l ess than 15 pf (except ea is 25 pf). 11. the input threshold voltage of p1.6 and p1.7 (sio1) meets the i 2 c specification, so an input voltage below 1.5 v will be recognized as a logic 0 while an input voltage above 3.0 v will be recognized as a logic 1.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 77 ac electrical characteristics (6 clock mode) t amb = 0 c to +70 c, v cc = 5 v 10% or 40 c to +85 c, v cc = 5 v 5%, v ss = 0 v 1, 2, 3 variable clock 4 20 mhz clock 4 symbol figure parameter min max min max unit 1/t clcl 57 oscillator frequency 0 20 mhz t lhll 57 ale pulse width t clcl 40 10 ns t avll 57 address valid to ale low 0.5t clcl 20 5 ns t llax 57 address hold after ale low 0.5t clcl 20 5 ns t lliv 57 ale low to valid instruction in 2t clcl 65 35 ns t llpl 57 ale low to psen low 0.5t clcl 20 5 ns t plph 57 psen pulse width 1.5t clcl 45 30 ns t pliv 57 psen low to valid instruction in 1.5t clcl 60 15 ns t pxix 57 input instruction hold after psen 0 0 ns t pxiz 57 input instruction float after psen 0.5t clcl 20 5 ns t aviv 57 address to valid instruction in 2.5t clcl 80 45 ns t plaz 57 psen low to address float 10 10 ns data memory t rlrh 58, 59 rd pulse width 3t clcl 100 50 ns t wlwh 58, 59 wr pulse width 3t clcl 100 50 ns t rldv 58, 59 rd low to valid data in 2.5t clcl 90 35 ns t rhdx 58, 59 data hold after rd 0 0 ns t rhdz 58, 59 data float after rd t clcl 20 5 ns t lldv 58, 59 ale low to valid data in 4t clcl 150 50 ns t avdv 58, 59 address to valid data in 4.5t clcl 165 60 ns t llwl 58, 59 ale low to rd or wr low 1.5t clcl 50 1.5t clcl +50 25 125 ns t avwl 58, 59 address valid to wr low or rd low 2t clcl 75 25 ns t qvwx 58, 59 data valid to wr transition 0.5t clcl 25 0 ns t whqx 58, 59 data hold after wr 0.5t clcl 20 5 ns t qvwh 59 data valid to wr high 3.5t clcl 130 45 ns t rlaz 58, 59 rd low to address float 0 0 ns t whlh 58, 59 rd or wr high to ale high 0.5t clcl 20 0.5t clcl +20 5 45 ns external clock t chcx 61 high time 20 t clcl t clcx ns t clcx 61 low time 20 t clcl t chcx ns t clch 61 rise time 5 ns t chcl 61 fall time 5 ns shift register t xlxl 60 serial port clock cycle time 6t clcl 300 ns t qvxh 60 output data setup to clock rising edge 5t clcl 133 117 ns t xhqx 60 output data hold after clock rising edge t clcl 30 20 ns t xhdx 60 input data hold after clock rising edge 0 0 ns t xhdv 60 clock rising edge to input data valid 5t clcl 133 117 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 3. interfacing the microcontroller to devices with float times up to 45ns is permitted. this limited bus contention will not cau se damage to port 0 drivers. 4. parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 78 ac electrical characteristics (6 clock mode) (continued) t amb = 0 c to +70 c, v cc = 5 v 10% or 40 c to +85 c,v cc = 5 v 5%, v ss = 0 v 1, 2 symbol parameter input output i 2 c interface t hd;sta start condition hold time 7 t clcl > 4.0 m s 4 t low scl low time 8 t clcl > 4.7 m s 46 t high scl high time 7 t clcl > 4.0 m s 4 t rc scl rise time 1 m s 5 t fc scl fall time 0.3 m s < 0.3 m s 6 t su;dat1 data set-up time 250 ns > 10 t clcl t rd t su;dat2 sda set-up time (before rep. start cond.) 250 ns > 1 m s 4 t su;dat3 sda set-up time (before stop cond.) 250 ns > 4 t clcl t hd;dat data hold time 0 ns > 4 t clcl t fc t su;sta repeated start set-up time 7 t clcl 4 > 4.7 m s 4 t su;sto stop condition set-up time 7 t clcl 4 > 4.0 m s 4 t buf bus free time 7 t clcl 4 > 4.7 m s 4 t rd sda rise time 1 m s 7 5 t fd sda fall time 300 ns 7 < 0.3 m s 6 notes: 1. parameters are valid over operating temperature range and voltage range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 3. these values are characterized but not 100% production tested. 4. at 100 kbit/s. at other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 5. determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 m s. 6. spikes on the sda and scl lines with a duration of less than 3 t clcl will be filtered out. maximum capacitance on bus-lines sda and scl = 400 pf. 7. t clcl = 1/f osc = one oscillator clock period at pin xtal1.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 79 ac electrical characteristics (12 clock mode) t amb = 0 c to +70 c, v cc = 5 v 10%, or 40 c to +85 c, v cc = 5 v 5%, v ss = 0v 1, 2, 3 variable clock 4 33 mhz clock 4 symbol figure parameter min max min max unit 1/t clcl 57 oscillator frequency 0 33 mhz t lhll 57 ale pulse width 2t clcl 40 21 ns t avll 57 address valid to ale low t clcl 25 5 ns t llax 57 address hold after ale low t clcl 25 5 ns t lliv 57 ale low to valid instruction in 4t clcl 65 55 ns t llpl 57 ale low to psen low t clcl 25 5 ns t plph 57 psen pulse width 3t clcl 45 45 ns t pliv 57 psen low to valid instruction in 3t clcl 60 30 ns t pxix 57 input instruction hold after psen 0 0 ns t pxiz 57 input instruction float after psen t clcl 25 5 ns t aviv 57 address to valid instruction in 5t clcl 80 70 ns t plaz 57 psen low to address float 10 10 ns data memory t rlrh 58, 59 rd pulse width 6t clcl 100 82 ns t wlwh 58, 59 wr pulse width 6t clcl 100 82 ns t rldv 58, 59 rd low to valid data in 5t clcl 90 60 ns t rhdx 58, 59 data hold after rd 0 0 ns t rhdz 58, 59 data float after rd 2t clcl 28 32 ns t lldv 58, 59 ale low to valid data in 8t clcl 150 90 ns t avdv 58, 59 address to valid data in 9t clcl 165 105 ns t llwl 58, 59 ale low to rd or wr low 3t clcl 50 3t clcl +50 40 140 ns t avwl 58, 59 address valid to wr low or rd low 4t clcl 75 45 ns t qvwx 58, 59 data valid to wr transition t clcl 30 0 ns t whqx 58, 59 data hold after wr t clcl 25 5 ns t qvwh 59 data valid to wr high 7t clcl 130 80 ns t rlaz 58, 59 rd low to address float 0 0 ns t whlh 58, 59 rd or wr high to ale high t clcl 25 t clcl +25 5 55 ns external clock t chcx 61 high time 17 t clcl t clcx ns t clcx 61 low time 17 t clcl t chcx ns t clch 61 rise time 5 ns t chcl 61 fall time 5 ns shift register t xlxl 60 serial port clock cycle time 12t clcl 360 ns t qvxh 60 output data setup to clock rising edge 10t clcl 133 167 ns t xhqx 60 output data hold after clock rising edge 2t clcl 80 50 ns t xhdx 60 input data hold after clock rising edge 0 0 ns t xhdv 60 clock rising edge to input data valid 10t clcl 133 167 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 3. interfacing the microcontroller to devices with float times up to 45 ns is permitted. this limited bus contention will not ca use damage to port 0 drivers. 4. parts are tested to 3.5 mhz, but guaranteed to operate down to 0 hz.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 80 ac electrical characteristics (12 clock mode) (continued) t amb = 0 c to +70 c, v cc = 5 v 10%, or 40 c to +85 c, v cc = 5 v 5%, v ss = 0 v 1, 2 symbol parameter input output i 2 c interface t hd;sta start condition hold time 14 t clcl > 4.0 m s 4 t low scl low time 16 t clcl > 4.7 m s 4 t high scl high time 14 t clcl > 4.0 m s 4 t rc scl rise time 1 m s 5 t fc scl fall time 0.3 m s < 0.3 m s 6 t su;dat1 data set-up time 250 ns > 20 t clcl t rd t su;dat2 sda set-up time (before rep. start cond.) 250 ns > 1 m s 4 t su;dat3 sda set-up time (before stop cond.) 250 ns > 8 t clcl t hd;dat data hold time 0 ns > 8 t clcl t fc t su;sta repeated start set-up time 14 t clcl 4 > 4.7 m s 4 t su;sto stop condition set-up time 14 t clcl 4 > 4.0 m s 4 t buf bus free time 14 t clcl 4 > 4.7 m s 4 t rd sda rise time 1 m s 7 5 t fd sda fall time 300 ns 7 < 0.3 m s 6 notes: 1. parameters are valid over operating temperature range and voltage range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 3. these values are characterized but not 100% production tested. 4. at 100 kbit/s. at other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 5. determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 m s. 6. spikes on the sda and scl lines with a duration of less than 3 t clcl will be filtered out. maximum capacitance on bus-lines sda and scl = 400 pf. 7. t clcl = 1/f osc = one oscillator clock period at pin xtal1. for 63 ns < t clcl < 285 ns (16 mhz > f osc > 3.5 mhz) the i 2 c interface meets the i 2 c-bus specification for bit-rates up to 100 kbit/s.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 81 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t lhll t plph t lliv t plaz t llpl t aviv su00006 t pliv figure 57. external program memory read cycle ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00025 figure 58. external data memory read cycle
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 82 t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx t qvwh su00026 figure 59. external data memory write cycle 012345678 instruction ale clock output data write to sbuf input data clear ri set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 123 0 4567 valid valid valid valid valid valid valid valid figure 60. shift register mode timing v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 61. external clock drive
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 83 v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00717 figure 62. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00718 figure 63. float waveform 2 4 6 8 10 12 14 16 18 60 50 40 30 20 10 frequency at xtal1 (mhz, 6 clock mode) i cc (ma) 89c660/662/664/668 maximum active i cc typical active i cc maximum idle typical idle su01402 20 70 figure 64. i cc vs. freq valid only within frequency specifications of the device under test
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 84 t rd t su;sta t buf t su;sto 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t fd t rc t fc t high t low t hd;sta t su;dat1 t hd;dat t su;dat2 t su;dat3 start condition repeated start condition sda (input/output) scl (input/output) stop condition start or repeated start condition su00107a figure 65. timing si01 (i 2 c) interface v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00010 figure 66. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00011 figure 67. float waveform
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 85 v cc p0 ea rst xtal1 xtal2 v ss v cc v cc v cc i cc (nc) clock signal p1.6 p1.7 * * 89c660 89c662 89c664 89c668 su01261 figure 68. i cc test condition, active mode. all other pins are disconnected v cc p0 rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal p1.6 p1.7 ea * * 89c660 89c662 89c664 89c668 su01262 figure 69. i cc test condition, idle mode. all other pins are disconnected v cc 0.5 0.5v t chcl t clcl t clch t clcx t chcx su00266 figure 70. clock signal waveform for i cc tests in active and idle modes. t clcl = t chcl = 10 ns v cc p0 rst xtal1 xtal2 v ss v cc v cc i cc (nc) p1.6 p1.7 ea * * 89c660 89c662 89c664 89c668 su01263 figure 71. i cc test condition, power-down mode. all other pins are disconnected; v cc = 2v to 5.5v note: * ports 1.6 and 1.7 should be connected to v cc through resistors of sufficiently high value such that the sink current into these pins does not exceed the i ol1 specification.
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 86 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 87 lqfp44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 88 revision history rev date description _4 20021028 product data (9397 750 10403); replaces p89c660/p89c662/p89c664 of 2001 jul 19 (9397 750 08584) and p89c668 of 2001 jul 27 (9397 750 08651) engineering change notice 8532392 29118 (date: 20021028) modifications: ? ?????????? ??MM ?? ??MM ????????? ? ????? ??? ?????????? ?? ? ? ? ???? ??? ???? ? ??? ???????? ??? ? ??M ??? ? ???? ?? ???????? ??? ??? ?????? ? ???????? ??? ????????
philips semiconductors product data p89c660/p89c662/p89c664/ p89c668 80c51 8-bit flash microcontroller family 16kb/32kb/64kb isp/iap flash with 512b/1kb/2kb/8kb ram 2002 oct 28 89 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2002 all rights reserved. printed in u.s.a. date of release: 10-02 document order number: 9397 750 10403

data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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